[llvm-testresults] Cron <andrewl at fenris> sh /home/andrewl/llvm-alpha.sh

Cron Daemon root at fenris.cs.uiuc.edu
Thu Jan 19 08:19:17 PST 2006


DEJAGNU TEST RESULTS:
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CFrontend/2004-06-17-UnorderedCompares.c.tr: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CFrontend/2005-12-04-AttributeUsed.c: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/CFrontend/2006-01-16-BitCountIntrinsicsUnsigned.c: 
  FAIL: /localhome/andrewl/test-alpha/llvm/test/Regression/ExecutionEngine/2003-01-04-ArgumentBug.ll: 

DEJAGNU STATISTICS:
  # of expected passes		1222
  # of unexpected failures	5
  # of expected failures		35
REMOVED WARNINGS:
lib/AsmParser//usr/share/bison.simple:: warning: comparison between signed and unsigned integer expressions
lib/AsmParser//usr/share/bison.simple:: warning: comparison between signed and unsigned integer expressions

cvs history: CVS password file /home/andrewl/.cvspass does not exist - creating a new file

TESTS FIXED:  

llc /MultiSource/Applications/SPASS/SPASS
llc-beta /MultiSource/Applications/SPASS/SPASS



USERS WHO COMMITTED:
  alenhar2
  evancheng
  jlaskey
  lattner
  reid
  sampo

ADDED FILES:
  llvm/test/Regression/CodeGen/Alpha/2006-01-18-MissedGlobal.ll
  llvm/test/Regression/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
  llvm/test/Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll

CHANGED FILES:
  llvm/include/llvm/Assembly/AutoUpgrade.h
  llvm/include/llvm/CodeGen/DwarfWriter.h
  llvm/lib/AsmParser/llvmAsmParser.cpp
  llvm/lib/AsmParser/llvmAsmParser.h
  llvm/lib/AsmParser/llvmAsmParser.y
  llvm/lib/Bytecode/Reader/Reader.cpp
  llvm/lib/CodeGen/DwarfWriter.cpp
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/PowerPC/README.txt
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Transforms/IPO/Internalize.cpp
  llvm/lib/Transforms/Utils/CloneModule.cpp
  llvm/lib/VMCore/AutoUpgrade.cpp
  llvm/lib/VMCore/Verifier.cpp
  llvm/test/Feature/intrinsics.ll
  llvm/utils/TableGen/DAGISelEmitter.cpp




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