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<p class="MsoNormal">The reason is that storing to EDI actually overwrites the upper 32 bits of RDI, so the EDI and RDI are considered identical in terms of register units.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Consolas">-- </span>
<span style="font-size:9.0pt;font-family:Consolas"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:8.0pt;font-family:Consolas">Krzysztof Parzyszek
<a href="mailto:kparzysz@quicinc.com">kparzysz@quicinc.com</a> AI tools development<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Constable, Scott D <scott.d.constable@intel.com>
<br>
<b>Sent:</b> Monday, January 24, 2022 3:11 PM<br>
<b>To:</b> Krzysztof Parzyszek <kparzysz@quicinc.com><br>
<b>Cc:</b> via llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> RE: [RDF] Question about function argument registers on X86<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p align="center" style="text-align:center"><strong><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;background:yellow">WARNING:</span></strong><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;background:yellow">
This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Intel Clear"">Thank you very much for the explanation, Krzysztof. There is still one part that I am missing. In the example below, RDF generates defs for DIL (bits 0:7 of RDI), DIH (bits 8:15 of RDI), and HDI (bits
16:31 of RDI). Hence bits 32:63 are unaccounted. Could this cause any issues? For example, suppose the program writes to RDI, and then clobbers EAX, but then the upper half of RDI is still defined.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">Scott<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
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<p class="MsoNormal"><b>From:</b> Krzysztof Parzyszek <<a href="mailto:kparzysz@quicinc.com">kparzysz@quicinc.com</a>>
<br>
<b>Sent:</b> Monday, January 24, 2022 11:48 AM<br>
<b>To:</b> Constable, Scott D <<a href="mailto:scott.d.constable@intel.com">scott.d.constable@intel.com</a>><br>
<b>Cc:</b> via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br>
<b>Subject:</b> RE: [RDF] Question about function argument registers on X86<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi Scott,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">It used to be the case early on that we’d create an entry for the register as it was specified, but I’ve been running into all sorts of complications when calculating liveness. Specifically, when defs/uses of “large” registers were intermingled
with defs/uses of their sub-registers, various “interesting” scenarios showed up. They had to do with representing unions/intersections of registers in terms of actual registers[1]---that was the reason for switching to tracking register units instead (see
RegisterAggr class).<o:p></o:p></p>
<p class="MsoNormal">The consequence of that is that the graph looks more cluttered, but things are easier to express accurately.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">[1] This was before lane masks became popular. Say we have<o:p></o:p></p>
<p class="MsoNormal">AX = def<o:p></o:p></p>
<p class="MsoNormal">AH = clobber<o:p></o:p></p>
<p class="MsoNormal">Here AX is still “defined” since some part of it is defined. Now, if we know that AX is “defined” then what can we say about it after executing “AL = clobber”? Turns out that this is difficult to answer, because we’d have to know the
history of how AX was modified, which isn’t always analyzed in full: (RDF stop def traversal at a PHI node).<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Consolas">-- <o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:8.0pt;font-family:Consolas">Krzysztof Parzyszek
<a href="mailto:kparzysz@quicinc.com">kparzysz@quicinc.com</a> AI tools development<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> llvm-dev <<a href="mailto:llvm-dev-bounces@lists.llvm.org">llvm-dev-bounces@lists.llvm.org</a>>
<b>On Behalf Of </b>Constable, Scott D via llvm-dev<br>
<b>Sent:</b> Saturday, January 22, 2022 3:24 PM<br>
<b>To:</b> <a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br>
<b>Subject:</b> [llvm-dev] [RDF] Question about function argument registers on X86<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p align="center" style="text-align:center"><strong><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;background:yellow">WARNING:</span></strong><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;background:yellow">
This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Intel Clear"">Hi,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">Given the function:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">long simpleExample(long x) {<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""> return x;<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">}<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">RDF produces the following data-flow graph:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">DFG dump:[<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">f1: Function: simpleExample<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">b2: --- %bb.0 --- preds(0): succs(0):<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">p8: phi [+d9<DIH:0000000000000001>(,,u15"):]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">p10: phi [+d11<DIL:0000000000000001>(,,u14"):]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">p12: phi [+d13<HDI:0000000000000001>(,,u5"):]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">s3: COPY [d4<RAX>(,,u7):, u5"<RDI>(+d13):, u14"<RDI>(+d11):, u15"<RDI>(+d9):]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">s6: RET [u7<RAX>!(d4):]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">]<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">Why is the argument in RDI split into three lanes that do not fully span RDI? It would seem more natural to just have a single phi for RDI.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">I think the RDF code responsible for this behavior is located here:
<a href="https://github.com/llvm/llvm-project/blob/55d887b833646baeea0e3371fd2cbbd7550a8d4d/llvm/lib/CodeGen/RDFGraph.cpp#L903">
https://github.com/llvm/llvm-project/blob/55d887b833646baeea0e3371fd2cbbd7550a8d4d/llvm/lib/CodeGen/RDFGraph.cpp#L903</a>, but I admit I do not fully understand what is going on.
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">Thanks in advance,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear"">Scott Constable<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Intel Clear""><o:p> </o:p></span></p>
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