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One problem is that the predicate in your PatFrag is defined in terms of SDNode, which won't work for GISel. Try adding a GISelPredicateCode to do the equivalent test on Machine IR. See also
<a href="https://llvm.org/docs/GlobalISel/InstructionSelect.html" id="LPNoLPOWALinkPreview">
https://llvm.org/docs/GlobalISel/InstructionSelect.html</a> (especially regarding SD imports).</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> llvm-dev <llvm-dev-bounces@lists.llvm.org> on behalf of Adrian Tong via llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Sent:</b> Monday, January 10, 2022 11:33 PM<br>
<b>To:</b> LLVM Developers Mailing List <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> [llvm-dev] AArch64 global isel</font>
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<div>Hi</div>
<div>I am writing a pattern to select ushr+or into usra on AArch64. I changed the following pattern from add to add_and_or_is_add. One test case test/CodeGen/AArch64/GlobalISel/combine-udiv.ll that uses global isel starts to fail and what was selected into
usra is now selected into ushr+add. This only happens in global isel, how can i debug this ?<br>
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<div>6471 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",<br>
6472 TriOpFrag<(add_and_or_is_add /* changed from add */ node:$LHS,<br>
6473 (AArch64vlshr node:$MHS, node:$RHS))>>;<br>
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<div>6345 // Match add node and also treat an 'or' node is as an 'add' if the or'ed operands<br>
6346 // have no common bits.<br>
6347 def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),<br>
6348 [(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{<br>
6349 if (N->getOpcode() == ISD::ADD)<br>
6350 return true;<br>
6351 return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));<br>
6352 }]>;<br>
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<div>Thanks </div>
<div>-Adrian</div>
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