<div dir="ltr"><div>I think ADDWrr is the scalar instruction. The pattern needs a different instruction name for the SIMD version of add. It might be ADDv16i8 but I don't know for sure.</div>
<br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Wed, Dec 8, 2021 at 9:25 AM Adrian Tong via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Hi<div><br></div><div>I would like to create a special case match pattern for OR instruction in AArch64 (Turn it into ADD). I am kind of new to table-gen and AArch64. It seems the first pattern with GPR32 works, but not the second pattern with SIMD registers.</div><div><br></div><div>def special_rule_for_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{<br> return trueOrFalse(); // return true or false depending on a set of rules.<br>}]>;<br></div><div><br></div><div>def : Pat<(special_rule_for_or GPR32:$src1, GPR32:$src2),<br> (ADDWrr GPR32:$src1, GPR32:$src2)>;<br><br>def : Pat<(special_rule_for_or (v16i8 FPR128:$src1), (v16i8 FPR128:$src2)),<br> (ADDWrr (v16i8 FPR128:$src1), (v16i8 FPR128:$src2))>;<br></div><div><br></div><div><div>This is the error I am seeing now.</div><div>>>>>>>>>></div><div>Type set is empty for each HW mode:</div><div>possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).<br>anonymous_9036: (ADDWrr:{ *:[i32] } FPR128:{ *:[] }:$src1, FPR128:{ *:[v16i8] }:$src2)<br>Generated from record:<br>anonymous_9036 { // Pattern Pat<br> dag PatternToMatch = (or_is_add (v16i8 FPR128:$src1), (v16i8 FPR128:$src2));<br> list<dag> ResultInstrs = [(ADDWrr (v16i8 FPR128:$src1), (v16i8 FPR128:$src2))];<br> list<Predicate> Predicates = [];<br> int AddedComplexity = 0;<br>}<br>Included from /usr/local/google/home/adriantong/opensource/llvm-project/llvm/lib/Target/AArch64/AArch64.td:538:<br>/usr/local/google/home/adriantong/opensource/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.td:8229:1: error: Type set is empty for each HW mode in 'anonymous_9036'<br></div><div><<<<<<<<<<</div><div><br></div><div>Thanks !</div><div><br></div></div></div>
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