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[AMD Official Use Only]<br>
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TL;DR
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<div>We propose the following change to LLVM IR:</div>
<div>- Allow bitcast to support no-op pointer cast between pointers from different address spaces.</div>
<div>- This bitcast is valid if the bit widths queried for addressspaces from datalayout match.</div>
<div>- Overload CastIsValid call with datalayout argument to check validity of cast.</div>
<div>- Update CastIsValid to allow bitcast between vector of pointers from different address spaces if total bit widths match.</div>
<div>- GVN pass introduces ptrtoint/inttoptr for load which reinterprets bits from previous store.
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<div> Instead use a no-op bitcast of ptrs from different address spaces.</div>
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<div>Motivation</div>
<div>==========</div>
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<div>When addrspacecast was introduced, abilty to do no-op pointer bitcast from different address spaces has been removed.</div>
<div>Pointer sizes are always known from DataLayout which is now made mandatory in LLVM IR.
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<div>So, Bitcast can be analysed to be no-op cast by matching the pointer sizes from DataLayout.</div>
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<div>Since there is no other way to do no-op reinterpret of bits, in some cases GVN pass introduces a ptrtoint/inttoptr pair.</div>
<div>After proper analysis, that a no-op bitcast can be done is concluded, then a bitcast can be introduced.</div>
<div>Usage of no-op pointer bitcast between addrspaces can be restricted to be used only by IR Transform passes but not by frontend.</div>
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<div>For example consider the below IR:</div>
<div>GVN pass has discovered a reinterpretation of bits via a store followed by a load.</div>
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<div>%struct.S.coerce = type { i32 addrspace(1)* }</div>
<div>%s.sroa.0 = alloca i32*, align 8, addrspace(5)</div>
<div>%0 = extractvalue %struct.S.coerce %s.coerce, 0</div>
<div>%1 = bitcast i32* addrspace(5)* %s.sroa.0 to i32 addrspace(1)* addrspace(5)*</div>
<div>%2 = addrspacecast i32 addrspace(1)* addrspace(5)* %1 to i32 addrspace(1)</div>
<div>store i32 addrspace(1)* %0, i32 addrspace(1) %2, align 8</div>
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<div>%3 = load i32*, i32* addrspace(5)* %s.sroa.0, align 8, !tbaa !2</div>
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<div>;GVN pass currently introduces no-op ptrotoint/inttoptr for load.</div>
<div>%3 = ptrtoint i32 addrspace(1)* %0 to i64</div>
<div>%4 = inttoptr i64 %3 to i32*</div>
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<div>;If bitcast of pointers from different address is allowed, load can be replaced with no-op bitcast</div>
<div>%3 = bitcast i32 addrspace(1)* %0 to i32*</div>
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<div>Implementation</div>
<div>==============</div>
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<div>1. There are certain cases where standalone instructions are created without linking them to basicblock/function or module.
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<div> In such cases DataLayout is not accessible by querying the module. To check validity of bitcast datalayout is mandatory.</div>
<div> So CastInst::CastIsValid, CastInst::create etc have been overloaded to take DataLayout as argument.</div>
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<div> static bool castIsValid(Instruction::CastOps op, Value *S, Type *DstTy,</div>
<div> const DataLayout &DL);</div>
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<div> static CastInst *Create(</div>
<div> Instruction::CastOps, ///< The opcode of the cast instruction</div>
<div> Value *S, ///< The value to be casted (operand 0)</div>
<div> Type *Ty, ///< The type to which cast should be made</div>
<div> const DataLayout &DL, ///< DataLayout to check validity of bitcast</div>
<div> const Twine &Name = "", ///< Name for the instruction</div>
<div> Instruction *InsertBefore = nullptr ///< Place to insert the instruction</div>
<div> );</div>
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<div>2. Verifier has been updated to check for validity of bitcast using datalayout.</div>
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<div>3. GVN pass has been updated to use bitcast for a load instead of emitting ptrtoint/<span style="background-color:rgb(255, 255, 255);display:inline !important"><span> </span>inttoptr.</span></div>
<div> llvm/lib/Transforms/Utils/VNCoercion.cpp</div>
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<div>Review link: <a href="https://reviews.llvm.org/D114533" id="LPlnkOWALinkPreview">
https://reviews.llvm.org/D114533</a> </div>
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<a target="_blank" id="LPUrlAnchor988765" href="https://reviews.llvm.org/D114533" style="text-decoration: none; color: var(--themePrimary);">⚙ D114533 LLVM IR should allow bitcast between address spaces with the same size.</a></div>
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LLVM IR should allow bitcast between address spaces with the same size.</div>
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reviews.llvm.org</div>
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<div>Regards,</div>
Chaitanya<br>
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