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<p class="MsoNormal">Thanks all for the responses.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’ve uploaded a provisional diff here:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><a href="https://reviews.llvm.org/D113150">https://reviews.llvm.org/D113150</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">JB<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Krzysztof Parzyszek <kparzysz@quicinc.com> <br>
<b>Sent:</b> Friday, October 29, 2021 2:26 PM<br>
<b>To:</b> Nagurne, James <j-nagurne@ti.com>; llvm-dev@lists.llvm.org<br>
<b>Subject:</b> [EXTERNAL] RE: RFC: Generalizing Hexagon's VLIWMachineScheduler<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">If you have a patch somewhere, we can give it a try.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Consolas">-- <o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:8.0pt;font-family:Consolas">Krzysztof Parzyszek
<a href="mailto:kparzysz@quicinc.com"><span style="color:#0563C1">kparzysz@quicinc.com</span></a> AI tools development<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> llvm-dev <<a href="mailto:llvm-dev-bounces@lists.llvm.org">llvm-dev-bounces@lists.llvm.org</a>>
<b>On Behalf Of </b>Nagurne, James via llvm-dev<br>
<b>Sent:</b> Friday, October 29, 2021 11:59 AM<br>
<b>To:</b> 'llvm-dev@lists.llvm.org' <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br>
<b>Subject:</b> [llvm-dev] RFC: Generalizing Hexagon's VLIWMachineScheduler<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p align="center" style="text-align:center"><strong><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;background:yellow">WARNING:</span></strong><span style="font-size:10.5pt;font-family:"Arial",sans-serif;color:black;background:yellow">
This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.</span><o:p></o:p></p>
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<p class="MsoNormal">The VLIW-aware pre-allocation scheduler used by Hexagon is a mostly-generic alternative to the default MachineScheduler implementation that attempts to order instructions in such a way as to optimize the number of instructions issued per
cycle. It does this by tracking available resources (DFAPacketizer) and balancing register pressure. This is a departure from the default list scheduler, which has no resource tracking and does not attempt to model instructions executing in parallel, instead
optimizing the straight-line path length of the DAG.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><a href="https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h">https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h</a><o:p></o:p></p>
<p class="MsoNormal"><a href="https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp">https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I intend to generalize these data structures…<o:p></o:p></p>
<p class="MsoNormal">* VLIWResourceModel<o:p></o:p></p>
<p class="MsoNormal">* VLIWMachineScheduler<o:p></o:p></p>
<p class="MsoNormal">* ConvergingVLIWScheduler<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">…by encapsulating Hexagon-specific behavior in virtual overloads of a generic API. There are only a couple places where target-specific behavior is explicit. These are identified quickly by uses of HexagonInstrInfo as identifier ‘QII’.
The algorithm itself is likely tuned specifically for Hexagon, but is still generally applicable.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The port is relatively straightforward, requiring only 3 overrides. Testing is less defined at the moment. I’m currently running a full LLVM regression, but this type of change certainly prefers performance regressions.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Are there any opinions on lifting this pass?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Are there any publicly available Hexagon benchmarks with which I can verify my changes? Alternatively, are any in the Hexagon development team available to test such a change internally?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">J.B. Nagurne<o:p></o:p></p>
<p class="MsoNormal">Code Generation<o:p></o:p></p>
<p class="MsoNormal">Texas Instruments<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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