<div class="__aliyun_email_body_block"><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Hi, Alex.</span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><br ></span></div><div  style="clear:both;">I think what you mentioned is XLenVT functional infra that avoids the duplication of the same <span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">non-W </span>instruction for RV32 and RV64. Could it be possible to keep <span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">XLenVT infra for <span  style="margin:.0px;padding:.0px;border:.0px;outline:.0px;color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;background-color:#ffffff;float:none;display:inline;">non-W </span><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">instruction to make it only one definition for both RV32 and RV64, and also one W instruction definition which only for RV64?</span></span></div><div  style="clear:both;"><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><br ></span></span></div><div  style="clear:both;"><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">Regards,</span></span></div><div  style="clear:both;"><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;"><span  style="color:#000000;font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;text-align:start;text-indent:.0px;text-transform:none;widows:2;background-color:#ffffff;text-decoration-thickness:initial;text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline;">Zeson</span></span></div><blockquote  style="margin-right:.0px;margin-top:.0px;margin-bottom:.0px;"><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">------------------------------------------------------------------</span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Sender:Alex Bradbury <asb@asbradbury.org></span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Sent At:2021 Sep. 20 (Mon.) 22:01</span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Recipient:Zeson <zixuan.wu@linux.alibaba.com></span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Cc:llvm-dev <llvm-dev@lists.llvm.org></span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Subject:Re: [llvm-dev] [SelectionDAG][RISCV] i32 type illegal in 64-bit target is really a good design in RISCV?</span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><br ></span></div>On Thu, 16 Sept 2021 at 11:22, Zeson via llvm-dev<br ><llvm-dev@lists.llvm.org> wrote:<br >><br >> Hi, all.<br >><br >> Considering the issue to leverage i32 series instructions, https://reviews.llvm.org/D107658. Also some other target DAG combine actions such as combining any_ext node to leverage ADDW/SUBW/...<br >> I think those effects are caused by originally and naturally treating i32 type illegal in 64-bit target for RISCV. And it makes much following work to add patches.<br >> Is it really a good way to handle i32 type in 64-bit mode RISCV target?<br >> Could it be just like what PowerPC does that make both i32 and i64 are legal in DAG selection phase?<br ><br >Hi Zeson,<br ><br >It's definitely a pain point for the RISC-V backend, though I would<br >highlight that making i32 a legal type and therefore duplicating all<br >instruction definitions for RV32 and RV64 has its own drawbacks<br >(repetition, possibility of surprising codegen differences for 32 vs<br >64-bit due to missing the duplicated instructions in instruction<br >patterns or elsewhere in the backend). You could of course argue that<br >those issues may be easier to debug and reason about than some of the<br >hassles with *W instructions.<br ><br >Please see <https://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html><br >for the initial RFC and discussion on this.<br ><br >I think ideally we would be able to maintain a single set of<br >parameterised instruction definitions (and I'd be keen to discuss any<br >ideas on making this easier to work with), but obviously if the<br >current implementation approach is causing more problems than it<br >solves we should be pragmatic.<br ><br >Best,<br ><br >Alex</blockquote><div ><br ></div></div>