<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Sep 17, 2021, at 12:00 PM, Francesco Bertolaccini <<a href="mailto:francesco@bertolaccini.dev" class="">francesco@bertolaccini.dev</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Thanks Quentin, it does help!<br class="">I'm referring to the docs at<br class=""><a href="https://llvm.org/docs/WritingAnLLVMBackend.html#register-set-and-register-classes" class="">https://llvm.org/docs/WritingAnLLVMBackend.html#register-set-and-register-classes</a><br class=""><br class="">How do register units play into the registers/register classes/register<br class="">sets described there?<br class=""><br class="">The situation I mentioned in my original mail would be implemented<br class="">something like this, if I am not mistaken:<br class=""><br class="">def A : Register<"A">;<br class="">def AB : Register<"AB"> {<br class=""> let SubRegs = [ A ];<br class="">};<br class="">def ABC : Register<"ABC"> {<br class=""> let SubRegs = [ AB ];<br class="">};<br class="">def ABCD : Register<"ABCD"> {<br class=""> let SubRegs = [ ABC ];<br class="">};<br class=""></div></div></blockquote><div><br class=""></div><div>Looks right to me.</div><br class=""><blockquote type="cite" class=""><div class=""><div class=""><br class="">Are the underlying register units automagically generated by TableGen?<br class=""></div></div></blockquote><div><br class=""></div><div>Yes the register units are automatically generated by TableGen.</div><div>You can see this in YourTargetGenRegisterInfo.inc in your build directory.</div><div>The <span style="font-family: Menlo; font-size: 11px;" class="">MCRegisterDesc </span>describes the register units for each register (5th field) (hard to see though :)).</div><div>And the full list of units stored in the variable YourTarget<span style="font-family: Menlo; font-size: 11px;" class="">RegUnitRoots</span>.</div><div><br class=""></div><div>Honestly, unless your needs are not covered by the existing APIs, I wouldn’t dig into that stuff. The way that stuff is represented is not super important.</div><div><br class=""></div><blockquote type="cite" class=""><div class=""><div class=""><br class="">Best regards,<br class="">Francesco<br class=""><br class="">On 17/09/2021 20:39, Quentin Colombet wrote:<br class=""><blockquote type="cite" class="">Hi Francesco,<br class=""><br class="">Yes, the subreg are transitive but the transitivity may not be<br class="">represented the way you expect.<br class=""><br class="">Essentially all the registers map to a set of register units. Two<br class="">registers overlap if their register units overlap.<br class="">The register units are not necessarily actual register.<br class=""><br class="">E.g., in your first example, ABCD maps to the reg unit A, B, C, and D.<br class="">In your second example, ADE maps to A and AD maps to A as well. Assuming<br class="">D and E are not physically accessible by themselves.<br class=""><br class="">You can take query the regunits using the related MCRegisterInfo API,<br class="">e.g., MCRegUnitIterator.<br class=""><br class="">Hope this helps.<br class=""><br class="">Cheers,<br class="">-Quentin<br class=""><br class=""></blockquote><br class=""></div></div></blockquote></div><br class=""></body></html>