<div class="__aliyun_email_body_block"><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Hi, all.</span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"><br ></span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;">Considering the issue to leverage i32 series instructions, https://reviews.llvm.org/D107658. Also some other target DAG combine actions such as combining any_ext node to leverage ADDW/SUBW/... </span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"> I think those effects are caused by originally and naturally treating i32 type illegal in 64-bit target for RISCV. And it makes much following work to add patches.</span></div><div  style="clear:both;"><span  style="font-family:Tahoma,Arial,STHeiti,SimSun;font-size:14.0px;color:#000000;"></span>Is it really a good way to handle i32 type in 64-bit mode RISCV target? </div><div  style="clear:both;">Could it be just like what PowerPC does that make both i32 and i64 are legal in DAG selection phase?</div><div  style="clear:both;"><br ></div><div  style="clear:both;"><br ></div><div  style="clear:both;"><br ></div><div  style="clear:both;">Regards,</div><div  style="clear:both;">Zeson</div></div>