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Hi Stefan.</div>
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<br>
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Thanks for the tip. But, it didn't do the trick - still only SSE. (the /proc/cpuinfo contains flag 'avx2')
<br>
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<br>
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I instrumented a bit:<br>
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JITTargetMachineBuilder JTMB((*TPC)->getTargetTriple());
<div><br>
</div>
<div> llvm::outs() << "feature string: " << JTMB.getFeatures().getString() << "\n";</div>
<div></div>
<div> llvm::outs() << "adding features...\n";</div>
<div> JTMB.addFeatures({"+avx2"});</div>
<div> </div>
<span> llvm::outs() << "feature string: " << JTMB.getFeatures().getString() << "\n";</span><br>
</div>
<div>
<div id="appendonsend"></div>
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<br>
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Output:<br>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Creating JIT
<div>feature string: </div>
<div>adding features...</div>
<div>feature string: +avx2</div>
Creating JIT successfu</div>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
But still only SSE:<br>
</div>
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<br>
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.Leval0_intern:
<div>.cfi_startproc</div>
<div>addl %esi, %edi</div>
<div>shll $3, %edi</div>
<div>movslq %edi, %rax</div>
<div>shlq $5, %rax</div>
<div>movaps (%r8,%rax), %xmm0</div>
<div>movaps 16(%r8,%rax), %xmm1</div>
<div>mulps 16(%rcx,%rax), %xmm1</div>
<div>mulps (%rcx,%rax), %xmm0</div>
<div>movaps %xmm0, (%rdx,%rax)</div>
<div>movaps %xmm1, 16(%rdx,%rax)</div>
<span>retq</span></div>
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<br>
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Should I switch to LLVM 13 release or is avx2 in JIT a trusted feature to be present in version 12?</div>
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Best,</div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Frank</div>
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<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Stefan Gränitz <stefan.graenitz@gmail.com><br>
<b>Sent:</b> Monday, August 30, 2021 5:00 PM<br>
<b>To:</b> Frank Winter <fwinter@jlab.org>; Craig Topper <craig.topper@gmail.com><br>
<b>Cc:</b> llvm-dev@lists.llvm.org <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm-dev] [EXTERNAL] Re: ORC JIT error when using AVX2 vector instructions</font>
<div> </div>
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<div>
<p style="margin-top: 0px; margin-bottom: 0px;">Hi Frank<br>
<br>
</p>
<blockquote type="cite">
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
That makes me think that the ORC JIT Kaleidoscope doesn't use the '+avx2' attribute.<br>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
How can ORC JIT Kaleidoscope generate jitted code with AVX2 instructions?</div>
</blockquote>
Did you try adding something like:<br>
JTMB.addFeatures({"+avx2"});<br>
<br>
Here?<br>
<a class="x_moz-txt-link-freetext" href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_llvm_llvm-2Dproject_blob_7a2a765745973ebeb041276d2d9489a000ba9371_llvm_examples_Kaleidoscope_BuildingAJIT_Chapter1_KaleidoscopeJIT.h-23L71&d=DwMD-g&c=CJqEzB1piLOyyvZjb8YUQw&r=tFpAzszScTWMAFcrGFW5xg&m=d7g1B6MAn9hV6ijrMKBgXHMYCQjKMfXQcxFZUzXsIIE&s=1xpxLmfuaVlN3_P_Uw-FHKkrxSRG2uXXxT44bMGkOWA&e=">https://github.com/llvm/llvm-project/blob/7a2a765745973ebeb041276d2d9489a000ba9371/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter1/KaleidoscopeJIT.h#L71</a><br>
<br>
Hope it helps.<br>
Best, Stefan<br>
<br>
<p style="margin-top: 0px; margin-bottom: 0px;"></p>
<div class="x_moz-cite-prefix">On 30/08/2021 21:46, Frank Winter via llvm-dev wrote:<br>
</div>
<blockquote type="cite">
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Thanks! Yeah, that was my silliness. Fixed and the module compiles now with ORC JIT Kaleidoscope.</div>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
However, looking at the assembler I only see SSE (128 bit vectors) being generated:</div>
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<br>
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.Leval0_intern:
<div>.cfi_startproc</div>
<div>addl %esi, %edi</div>
<div>shll $3, %edi</div>
<div>movslq %edi, %rax</div>
<div>shlq $5, %rax</div>
<div>movaps (%r8,%rax), %xmm0</div>
<div>movaps 16(%r8,%rax), %xmm1</div>
<div>mulps 16(%rcx,%rax), %xmm1</div>
<div>mulps (%rcx,%rax), %xmm0</div>
<div>movaps %xmm0, (%rdx,%rax)</div>
<div>movaps %xmm1, 16(%rdx,%rax)</div>
<span>retq</span></div>
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<br>
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I cross checked what LLC gives:</div>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Calling llc with no optional flags gives matching assembler, but when adding '-mattr=+avx2' I get AVX2 (256 bit vectors)<br>
</div>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
.Leval0_intern: # @eval0_intern
<div> .cfi_startproc</div>
<div># %bb.0: # %stack</div>
<div> addl %esi, %edi</div>
<div> shll $3, %edi</div>
<div> movslq %edi, %rax</div>
<div> shlq $5, %rax</div>
<div> vmovaps (%r8,%rax), %ymm0</div>
<div> vmulps (%rcx,%rax), %ymm0, %ymm0</div>
<div> vmovaps %ymm0, (%rdx,%rax)</div>
<div> vzeroupper</div>
<span> retq</span><br>
</div>
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<br>
</div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
That makes me think that the ORC JIT Kaleidoscope doesn't use the '+avx2' attribute.<br>
</div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
<br>
</div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
How can ORC JIT Kaleidoscope generate jitted code with AVX2 instructions?<br>
</div>
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<br>
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<div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Thanks again & Best wishes,</div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Frank</div>
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<br>
</div>
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<br>
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<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Craig Topper
<a class="x_moz-txt-link-rfc2396E" href="mailto:craig.topper@gmail.com"><craig.topper@gmail.com></a><br>
<b>Sent:</b> Monday, August 30, 2021 3:20 PM<br>
<b>To:</b> Frank Winter <a class="x_moz-txt-link-rfc2396E" href="mailto:fwinter@jlab.org">
<fwinter@jlab.org></a><br>
<b>Cc:</b> <a class="x_moz-txt-link-abbreviated" href="mailto:llvm-dev@lists.llvm.org">
llvm-dev@lists.llvm.org</a> <a class="x_moz-txt-link-rfc2396E" href="mailto:llvm-dev@lists.llvm.org">
<llvm-dev@lists.llvm.org></a><br>
<b>Subject:</b> [EXTERNAL] Re: [llvm-dev] ORC JIT error when using AVX2 vector instructions</font>
<div> </div>
</div>
<div>
<div dir="ltr">This is an illegal instruction. mul is an integer operation, but that has floating point types. The correct operation would be fmul.
<div><br>
</div>
<div><span style="color:rgb(0,0,0); font-family:Calibri,Arial,Helvetica,sans-serif; font-size:16px">%21 = mul <8 x float> %20, %10</span><br>
</div>
<div><br clear="all">
<div>
<div dir="ltr" class="x_x_gmail_signature">~Craig</div>
</div>
<br>
</div>
</div>
<br>
<div class="x_x_gmail_quote">
<div dir="ltr" class="x_x_gmail_attr">On Mon, Aug 30, 2021 at 12:08 PM Frank Winter via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<br>
</div>
<blockquote class="x_x_gmail_quote" style="margin:0px 0px 0px
0.8ex; border-left:1px solid rgb(204,204,204); padding-left:1ex">
<div dir="ltr">
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Hi.</div>
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As soon as the module contains instructions operating on < 8 x float > the ORC JIT refuses to work.</div>
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Here's the module that provokes the error given further below: <br>
</div>
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<br>
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<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
; ModuleID = 'module'
<div>source_filename = "module"</div>
<div>target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"</div>
<div><br>
</div>
<div>define private void @eval0_intern(i32 %arg0, i32 %arg1, <8 x float>* %arg2, <8 x float>* %arg3, <8 x float>* %arg4) {</div>
<div>stack:</div>
<div> br label %afterstack</div>
<div><br>
</div>
<div>afterstack: ; preds = %stack</div>
<div> %0 = add nsw i32 %arg0, %arg1</div>
<div> %1 = add nsw i32 0, %0</div>
<div> %2 = mul i32 %1, 1</div>
<div> %3 = add nsw i32 %2, 0</div>
<div> %4 = mul i32 %3, 1</div>
<div> %5 = add nsw i32 %4, 0</div>
<div> %6 = mul i32 %5, 1</div>
<div> %7 = add nsw i32 %6, 0</div>
<div> %8 = mul i32 %7, 8</div>
<div> %9 = getelementptr <8 x float>, <8 x float>* %arg3, i32 %8</div>
<div> %10 = load <8 x float>, <8 x float>* %9, align 32</div>
<div> %11 = add nsw i32 0, %0</div>
<div> %12 = mul i32 %11, 1</div>
<div> %13 = add nsw i32 %12, 0</div>
<div> %14 = mul i32 %13, 1</div>
<div> %15 = add nsw i32 %14, 0</div>
<div> %16 = mul i32 %15, 1</div>
<div> %17 = add nsw i32 %16, 0</div>
<div> %18 = mul i32 %17, 8</div>
<div> %19 = getelementptr <8 x float>, <8 x float>* %arg4, i32 %18</div>
<div> %20 = load <8 x float>, <8 x float>* %19, align 32</div>
<div> %21 = mul <8 x float> %20, %10</div>
<div> %22 = add nsw i32 0, %0</div>
<div> %23 = mul i32 %22, 1</div>
<div> %24 = add nsw i32 %23, 0</div>
<div> %25 = mul i32 %24, 1</div>
<div> %26 = add nsw i32 %25, 0</div>
<div> %27 = mul i32 %26, 1</div>
<div> %28 = add nsw i32 %27, 0</div>
<div> %29 = mul i32 %28, 8</div>
<div> %30 = getelementptr <8 x float>, <8 x float>* %arg2, i32 %29</div>
<div> store <8 x float> %21, <8 x float>* %30, align 32</div>
<div> ret void</div>
<div>}</div>
<div><br>
</div>
<div>define void @eval0(i32 %idx, [8 x i8]* %arg_ptr) {</div>
<div>entrypoint:</div>
<div> %0 = getelementptr [8 x i8], [8 x i8]* %arg_ptr, i32 0</div>
<div> %1 = bitcast [8 x i8]* %0 to i32*</div>
<div> %2 = load i32, i32* %1, align 4</div>
<div> %3 = getelementptr [8 x i8], [8 x i8]* %arg_ptr, i32 1</div>
<div> %4 = bitcast [8 x i8]* %3 to <8 x float>**</div>
<div> %5 = load <8 x float>*, <8 x float>** %4, align 8</div>
<div> %6 = getelementptr [8 x i8], [8 x i8]* %arg_ptr, i32 2</div>
<div> %7 = bitcast [8 x i8]* %6 to <8 x float>**</div>
<div> %8 = load <8 x float>*, <8 x float>** %7, align 8</div>
<div> %9 = getelementptr [8 x i8], [8 x i8]* %arg_ptr, i32 3</div>
<div> %10 = bitcast [8 x i8]* %9 to <8 x float>**</div>
<div> %11 = load <8 x float>*, <8 x float>** %10, align 8</div>
<div> call void @eval0_intern(i32 %idx, i32 %2, <8 x float>* %5, <8 x float>* %8, <8 x float>* %11)</div>
<div> ret void</div>
<div>}</div>
<div>--------------------------</div>
<div><br>
</div>
<div><br>
</div>
<div>For the JIT part I'm using the Kaleidoscope ORC JIT as given in the LLVM examples. However, when it comes to the symbol lookup the program stops with output like this:<br>
</div>
<div><br>
</div>
Lookup
<div>LLVM ERROR: Cannot select: 0x562e8bb6c268: v4f32 = mul 0x562e8bb6bab0, 0x562e8bb6b6a0</div>
<div> 0x562e8bb6bab0: v4f32,ch = load<(load 16 from %ir.19 + 16, basealign 32)> 0x562e8baf8ca8, 0x562e8bb6c130, undef:i64</div>
<div> 0x562e8bb6c130: i64 = add nuw 0x562e8bb6bcb8, Constant:i64<16></div>
<div> 0x562e8bb6bcb8: i64 = add 0x562e8bb6bc50, 0x562e8bb6b9e0</div>
<div> 0x562e8bb6bc50: i64,ch = CopyFromReg 0x562e8baf8ca8, Register:i64 %4</div>
<div> 0x562e8bb6bbe8: i64 = Register %4</div>
<div> 0x562e8bb6b9e0: i64 = shl 0x562e8bb6b910, Constant:i8<5></div>
<div> 0x562e8bb6b910: i64 = sign_extend 0x562e8bb6b770</div>
<div> 0x562e8bb6b770: i32 = shl 0x562e8bb6b500, Constant:i8<3></div>
<div> 0x562e8bb6b500: i32 = add nsw 0x562e8bb6b3c8, 0x562e8bb6b498</div>
<div> 0x562e8bb6b3c8: i32,ch = CopyFromReg 0x562e8baf8ca8, Register:i32 %0</div>
<div> 0x562e8bb6b360: i32 = Register %0</div>
<div> 0x562e8bb6b498: i32,ch = CopyFromReg 0x562e8baf8ca8, Register:i32 %1</div>
<div> 0x562e8bb6b430: i32 = Register %1</div>
<div> 0x562e8bb6ea28: i8 = Constant<3></div>
<div> 0x562e8bb6c2d0: i8 = Constant<5></div>
<div> 0x562e8bb6b638: i64 = Constant<16></div>
<div> 0x562e8bb6bb18: i64 = undef</div>
<div> 0x562e8bb6b6a0: v4f32,ch = load<(load 16 from %ir.9 + 16, basealign 32)> 0x562e8baf8ca8, 0x562e8bb6c198, undef:i64</div>
<div> 0x562e8bb6c198: i64 = add nuw 0x562e8bb6ba48, Constant:i64<16></div>
<div> 0x562e8bb6ba48: i64 = add 0x562e8bb6b8a8, 0x562e8bb6b9e0</div>
<div> 0x562e8bb6b8a8: i64,ch = CopyFromReg 0x562e8baf8ca8, Register:i64 %3</div>
<div> 0x562e8bb6b840: i64 = Register %3</div>
<div> 0x562e8bb6b9e0: i64 = shl 0x562e8bb6b910, Constant:i8<5></div>
<div> 0x562e8bb6b910: i64 = sign_extend 0x562e8bb6b770</div>
<div> 0x562e8bb6b770: i32 = shl 0x562e8bb6b500, Constant:i8<3></div>
<div> 0x562e8bb6b500: i32 = add nsw 0x562e8bb6b3c8, 0x562e8bb6b498</div>
<div> 0x562e8bb6b3c8: i32,ch = CopyFromReg 0x562e8baf8ca8, Register:i32 %0</div>
<div> 0x562e8bb6b360: i32 = Register %0</div>
<div> 0x562e8bb6b498: i32,ch = CopyFromReg 0x562e8baf8ca8, Register:i32 %1</div>
<div> 0x562e8bb6b430: i32 = Register %1</div>
<div> 0x562e8bb6ea28: i8 = Constant<3></div>
<div> 0x562e8bb6c2d0: i8 = Constant<5></div>
<div> 0x562e8bb6b638: i64 = Constant<16></div>
<span> 0x562e8bb6bb18: i64 = undef</span><br>
</div>
<div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
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The module compiles fine with LLC. So, I assume that's not the problem.</div>
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What might go wrong? Is there a way to initialize the ORC JIT with the AVX2 option somehow?<br>
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This is using LLVM release 12.<br>
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Best,</div>
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Frank</div>
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