<div style="line-height:1.7;color:#000000;font-size:14px;font-family:Arial"><div style="margin: 0;">Thanks! The problem has been solved.</div><div style="margin: 0;">Here comes another problem related to the previous one.</div><div style="margin: 0;">We know that ARM use struct to represent the relationship between SuperReg and SubReg in C level.</div><div style="margin: 0;">for example:</div><div style="margin: 0;">------------------------------------------------------------------------------</div><div style="margin: 0;">// this is file a.c</div><p style="margin: 0;">1 #include "arm_neon.h"</p><p style="margin: 0;">2 void test (float32_t *p1, float32_t *p2, float32_t *p3) {</p><p style="margin: 0;">3 float32x4x2_t a = vld1q_f32_x2(p1);</p><p style="margin: 0;">4 float32x4x2_t b = vld1q_f32_x2(p2);</p><p style="margin: 0;">5 float32x4_t c = vaddq_f32(a.val[0], b.val[1]);</p><p style="margin: 0;">6 vst1q_f32(p3, c);</p><p style="margin: 0;">7 }</p><div>-----------------------------------------------------------------------------</div><div>compiling the c source by "clang --target=aarch64 -O3 -S a.c" will generate a.s like below:</div><div>--------------------------------------------------------------------------------------------------------------------------------------</div><div> 1 .text</div><div> 2 .file "b.c"</div><div> 3 .globl test // -- Begin function test</div><div> 4 .p2align 2</div><div> 5 .type test,@function</div><div> 6test: // @test</div><div> 7.Ltest$local:</div><div> 8// %bb.0: // %entry</div><div> 9 ld1 { v0.4s, v1.4s }, [x0]</div><div>10 ld1 { v2.4s, v3.4s }, [x1]</div><div>11 fadd v0.4s, v0.4s, v3.4s</div><div>12 str q0, [x2]</div><div>13 ret</div><div>14.Lfunc_end0:</div><div>15 .size test, .Lfunc_end0-test</div><div>16 // -- End function</div><div>17 .ident "clang version 11.0.0 "</div><div>18 .section ".note.GNU-stack","",@progbits</div><div>19 .addrsig</div><div>----------------------------------------------------------------------------------------------------------------------------------------------</div><div style="margin: 0;">the definition of float32x4x2_t is:</div><div style="margin: 0;">------------------------------------------------------------------------</div><p style="margin: 0;">157 typedef struct float32x4x2_t {</p><p style="margin: 0;">158 float32x4_t val[2];</p><div style="margin: 0;">159 } float32x4x2_t;</div><div style="margin: 0;">-------------------------------------------------------------------------</div><div style="margin: 0;">vld1q_f32_x2 will load QQ which consists of two subreg (Q). So a.val[0] refers to the first SubReg Q and b.val[1] refers to the second SubReg Q.</div><div style="margin: 0;"><br></div><div style="margin: 0;">I need to implement something like this. A load builtin would load an QVR, which is represented by struct. like this</div><div style="margin: 0;"><div style="margin: 0px;">--------------------------------------------------------------------------------------------</div><div style="margin: 0px;">typedef struct dvr_t {</div><div style="margin: 0px;"> float32x4_t val[2];</div><div style="margin: 0px;">} dvr_t;</div><div style="margin: 0px;">typedef struct qvr_t {</div><div style="margin: 0px;"> dvr_t val[2];</div><div style="margin: 0px;">} qvr_t;</div><div style="margin: 0px;">--------------------------------------------------------------------------------------</div></div><div style="margin: 0;">and we can use qvr_t.val[0] to refer to the first SubReg DVR, qvr_t.val[1] to refer to the second SubReg DVR.</div><div style="margin: 0;">And also we can use qvr_t.val[0].val[0] to refer to the first VR SubReg, qvr_t.val[1].val[1] to refer to the fourth VR SubReg, and so on.</div><div style="margin: 0;">What is different is that ARM usage has one level inclusion in struct but the above usage has two level inclusion in struct.</div><div style="margin: 0;">I have been trying to find a solution for a few days. The key point is that I need load data into some QVR, and get the SubReg(VR or DVR) of the QVR loaded directly as operand for later operation.</div><div style="margin: 0;">Is there any soloution or idea for the problem? </div><div style="margin: 0;"><br></div><div style="margin: 0;">Many Thanks!</div><div style="margin: 0;"><br></div><div style="position:relative;zoom:1"></div><div id="divNeteaseMailCard"></div><p style="margin: 0;"><br></p><p>At 2021-08-10 22:51:37, "Diogo Sampaio" <dsampaio@kalray.eu> wrote:</p><blockquote id="isReplyContent" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid"><div style="font-size: 12pt; font-family: arial, helvetica, sans-serif; color: rgb(0, 0, 0);"><div style="font-size: 12pt; font-family: 'arial' , 'helvetica' , sans-serif; color: #000000;">
<div>We also had quad registers defined in function of 4 single registers, then we couldn't extract paired register from it easily.</div>
<div>So we changed and made them defined in function of paired registers. We also named the sub indices as to know what size of sub-register we want. Is something alike this:</div>
<div> </div>
<div>// Defining sub-register indexes</div>
<div>def sub_p0 : SubRegIndex<128, 0>;</div>
<div>def sub_p1 : SubRegIndex<128,128>;</div>
<div> </div>
<div>def sub_s0 : SubRegIndex<64, 0>;</div>
<div>def sub_s1 : SubRegIndex<64, 64>;</div>
<div>def sub_s2 : ComposedSubRegIndex<sub_p1, sub_s0>;</div>
<div>def sub_s3 : ComposedSubRegIndex<sub_p1, sub_s1>;</div>
<div> </div>
<div>// Composed register classes</div>
<div>
<div>// Paired Registers</div>
<div>class PGR<string n, list<Register> subregs></div>
<div> : : RegisterWithSubRegs<n, subregs> {</div>
<div> let SubRegIndices = [sub_s0, sub_s1];</div>
<div>}</div>
<div> </div>
<div>// Quad Register</div>
<div>
<div>class QGR<string n, list<Register> subregs></div>
<div> : RegisterWithSubRegs<n, subregs> {</div>
<div> let SubRegIndices = [sub_p0, sub_p1];</div>
<div>}</div>
<div> </div>
<div>// Defining registers</div>
<div>def P0 : PGR< 0, "$r0r1", [ R0, R1]>;</div>
<div>def P2 : PGR< 2, "$r2r3", [ R2, R3]>;</div>
<div>....</div>
<div> </div>
</div>
</div>
<div>def Q0 : QGR< 0, "$r0r1r2r3", [ P0, P2]>;</div>
<div> </div>
<div>//</div>
<div>Now can use any of those 6 sub-index to reference 2 sub-pair registers or any of the 4 single registers.</div>
<div>
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<div style="font-size: 9pt; font-family: 'arial' , 'helvetica' , sans-serif;"><span style="color: #4d4d4d; font-size: 9pt;"><strong>Diogo Sampaio</strong></span><br><span style="color: #11588f; font-size: 9pt;"><strong>Senior Compiler Engineer • Kalray</strong></span><br><span style="color: #4d4d4d; font-size: 8pt;">Phone: </span><br><span style="color: #11588f; font-size: 8pt;"><u>dsampaio@kalrayinc.com</u> • <a style="color: #11588f;" href="https://www.kalrayinc.com" target="_blank" rel="noopener noreferrer"><u>www.kalrayinc.com</u></a></span></div>
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<blockquote style="margin: 0 0 0 0.8em; border-left: 1px #ccc solid; padding-left: 1em;"><hr id="MESSAGE_DATA_MARKER"><strong>From: </strong>Fraser <llvm-dev@lists.llvm.org><br><strong>To: </strong>jackie <jackie_linzz@126.com><br><strong>Cc: </strong>llvm-dev <llvm-dev@lists.llvm.org><br><strong>Date: </strong>Tuesday, 10 August 2021 2:15 PM CEST<br><strong>Subject: </strong>Re: [llvm-dev] How to define subreg relationship in td file?<br><br>Hi,<br><br>You can (I'm hesitant to say you "must") model this with extra "fake"<br>(in some sense) physical registers which represent the paired and<br>quadrupled registers. This will also tell the register allocator that<br>allocating VRPair0 will clobber both VR0 *and VR1*, for example.<br><br>So you have half the number of VRPair registers which each have two VRs<br>as subregisters, then half that again of VRQuad registers which have<br>two VRPairs as subregisters. The subregister properties will apply<br>transitively so your VRQuads will have four VR subregisters using<br>composed subregister indices which LLVM will either automatically infer<br>or you can specify yourself with ComposedSubRegIndex.<br><br>Take a look at RISCVRegisterInfo.td for inspriation. Each vector V<br>register is paired into VM2 which are in turn paried into VM4s and then<br>into VM8s.<br><br>Cheers,<br>Fraser<br><br>On Tue, 2021-08-10 at 19:54 +0800, 林政宗 via llvm-dev wrote:<br>> Hi, there.<br>> <br>> I met a problem about defining SubReg relationship when defining<br>> Registers in td file.<br>> The target has a kind of vector register named VR which is of type<br>> v4f32. <br>> 2 VR makes 1 DVR. 4 VR makes 1 QVR.<br>> I have some code like this:<br>> -------------------------------------------------------------------<br>> -----------------------------------<br>> def VRPairs : RegisterTuples<[vsub_0, vsub_1],<br>> [(decimate (rotl VRegs, 0), 2),<br>> (decimate (rotl VRegs, 1), 2)],<br>> []>;<br>> <br>> def VRQuads : RegisterTuples<[vsub_0, vsub_1, vsub_2, vsub_3],<br>> [(decimate (rotl VRegs, 0), 4),<br>> (decimate (rotl VRegs, 1), 4),<br>> (decimate (rotl VRegs, 2), 4),<br>> (decimate (rotl VRegs, 3), 4)],<br>> []>;<br>> def DVRRegs : RegisterClass<"xxx", [v8f32], 256, (add VRPairs)>;<br>> <br>> def QVRRegs : RegisterClass<"xxx", [v16f32], 512, (add VRQuads)>;<br>> -------------------------------------------------------------------<br>> -----------------------------------<br>> But also, 2 DVR makes 1 QVR. QVR has two subregs, each of which is 1<br>> DVR.<br>> How can I describe the SubReg relationship between DVR and QVR? <br>> Could anyone help? Thanks in advance!<br>> <br>> <br>> BR,<br>> Jerry<br>> <br>> <br>> <br>> <br>> <br>> _______________________________________________<br>> LLVM Developers mailing list<br>> <a href="mailto:llvm-dev@lists.llvm.org" target="_blank" rel="noopener noreferrer">llvm-dev@lists.llvm.org</a><br>> <br>> <a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank" rel="noopener noreferrer">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><br>> <br><br>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:llvm-dev@lists.llvm.org" target="_blank" rel="noopener noreferrer">llvm-dev@lists.llvm.org</a><br><a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank" rel="noopener noreferrer">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><br>
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