<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Jun 21, 2021, at 10:05 AM, Nemanja Ivanovic via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">I am having a really difficult time with subregister related issues when I turn<br class="">on subregister liveness tracking.<br class=""><br class="">Before RA:<br class=""><span style="font-family:monospace" class="">79760B %2216:vsrc = LXVDSX %5551:g8rc_and_g8rc_nox0, %2215:g8rc :: (load 8 from %ir.scevgep1857.cast, !alias.scope !92, !noalias !93)<br class="">79872B %2225:vsrprc = LXVP 352, %661:g8rc_and_g8rc_nox0<br class="">84328B %5540:vsrc = contract nofpexcept XVMADDADP %5540:vsrc(tied-def 0), %2225.sub_vsx0:vsrprc, %2216:vsrc, implicit $rm<br class=""></span><br class="">After RA (greedy):<br class=""><span style="font-family:monospace" class="">79744B %2214:vsrc = LXVDSX %5551:g8rc_and_g8rc_nox0, %6477:g8rc :: (load 8 from %ir.scevgep1860.cast, !alias.scope !92, !noalias !93)<br class="">79872B %7503:vsrprc = LXVP 352, %661:g8rc_and_g8rc_nox0<br class="">80248B %7527:vsrprc = COPY %7503:vsrprc<br class="">80988B undef %7526.sub_64:vsrprc = COPY %7527.sub_64:vsrprc<br class="">84324B undef %7501.sub_64:vsrprc = COPY %7526.sub_64:vsrprc<br class="">84328B %5546:vsrc = contract nofpexcept XVMADDADP %5546:vsrc(tied-def 0), %7501.sub_vsx0:vsrprc, %2214:vsrc, implicit $rm<br class=""></span><br class="">Subregister definitions for PPC:<br class=""><span style="font-family:monospace" class="">def sub_64 : SubRegIndex<64>;<br class="">def sub_vsx0 : SubRegIndex<128>;<br class="">def sub_vsx1 : SubRegIndex<128, 128>;<br class="">def sub_pair0 : SubRegIndex<256>;<br class="">def sub_pair1 : SubRegIndex<256, 256>;<br class=""></span><br class="">So the instruction at 84328B uses the full register %2216 and the high order<br class="">128 bits of (256-bit) register %2225. However, the register allocator splits<br class="">the live range and introduces a copy of the high order 64 bits of that 256-bit<br class="">register, then another copy of that copy and rewrites the use in instruction<br class="">84328B to that copy. The copy is marked undef so the register allocator<br class="">assigns just some random register to the use of that copy in 84328B.<br class=""><br class="">Or maybe I am completely misinterpreting the meaning of the debug dumps<br class="">from the register allocator.<br class=""><br class="">This appears to be related to lane masks and dead lane detection although<br class="">I don't see dead lane detection marking anything unexpected as undef (seems<br class=""><div class="">to just be INSERT_SUBREG and PHI).</div></div></div></blockquote><div><br class=""></div><div>Are the copies added by dead lane detection or by live-range splitting?</div><div><br class=""></div><div>The undef flag on the definition of %7501 is suspicious and depending on how you look at it, so is the one on %7526. Essentially, we are losing the full copy in this chain of copies and I wonder what is at fault here.</div><div><br class=""></div>Could you share the debug output of regalloc?</div><div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div class=""><br class=""></div><div class="">If anyone has suggestions on what might be the issue and/or how to go about figuring this out and fixing it, I would really appreciate it.</div><div class=""><br class=""></div><div class="">Nemanja<br class=""></div></div>
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