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<p class="MsoNormal">I’m having an issue in a downstream target that I’m trying to track down and characterize involving a custom scheduling pass similar to Hexagon’s VLIW scheduler, and am looking for any tips on what I should be looking for.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Consider the following instructions taking place in program order in a MachineBasicBlock<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<ol style="margin-top:0in" start="1" type="1">
<li class="MsoListParagraph" style="margin-left:0in;mso-list:l2 level1 lfo1">$r1 = unrelated_instruction<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l2 level1 lfo1">DBG_VALUE $r0, $noreg, !”variable_name”<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l2 level1 lfo1">use $r0<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l2 level1 lfo1">…<o:p></o:p></li></ol>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">During the creation of the schedule DAG, ScheduleDAGInstrs::buildSchedGraph populates a list of MachineInstr pairs. Each pair is a debug instruction and the instruction immediately preceding it (again, before scheduling). Therefore, in
the above case, the list has a single member, the pair <2, 1> because the DBG_VALUE 2) has an immediate predecessor of 1).<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Scheduling then occurs. Because there is no edge between 1) and 3), I believe that the algorithm can legally schedule 3) before 1).<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Finally, placeDebugValues is called. This function takes each pair created in the above step and splices the DEBUG_VALUE into the block so that it immediately succeeds the instruction it succeeded prior to scheduling. This leaves us with
the new scheduled order:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<ol style="margin-top:0in" start="1" type="1">
<li class="MsoListParagraph" style="margin-left:0in;mso-list:l1 level1 lfo3">use $r0<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l1 level1 lfo3">$r1 = unrelated_instruction<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l1 level1 lfo3">DBG_VALUE $r0, $noreg, !”variable_name”<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l1 level1 lfo3">…<o:p></o:p></li></ol>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I can’t imagine that this is expected. The knowledge that the use of $0 in the new 1) is ‘variable_name’ is lost. Furthermore, we now have a strange liveness problem in that the DBG_VALUE is apparently killing $r0, which sounds logically
incorrect.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">To add one more level of specifics, the error I’m getting stems from the above plus the register kill fixup step that happens after each basic block is scheduled. Both the use of $r0 and the DBG_VALUE are added to a VLIW bundle, which inherits
register behaviors from the contained instructions:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">BUNDLE implicit $r0<o:p></o:p></p>
<p class="MsoNormal"> use $r0<o:p></o:p></p>
<p class="MsoNormal">BUNDLE implicit $r0<o:p></o:p></p>
<p class="MsoNormal"> DBG_VALUE $r0, $noreg, !”variable_name” <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">After the fixup step, both bundles are marked as kills of $r0, I believe as a consequence of the fact that the fixup step skips debug instructions at the top level, but not at the bundle level. This triggers the MachineVerifier to complain
that the bundle containing the DBG_VALUE is using an undefined register because the prior bundle killed it.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">J.B. Nagurne<o:p></o:p></p>
<p class="MsoNormal">Code Generation<o:p></o:p></p>
<p class="MsoNormal">Texas Instruments<o:p></o:p></p>
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