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<p class="MsoNormal">Thank Florian. I agree with you that pointers to `x86_amx` have different semantics than regular LLVM pointer types. First the x86_amx pointer point to a 2D array of a big matrix. The data of each row is contiguous, but the data on contiguous
row is not contiguous in memory. Below picture shows the x86_amx load semantics. We need another operand stride to describe the stride of each rows. So the semantics for “load <256xi32>*” and “load x86_amx” is different. Because “load <256 x i32>* assume
the memory is contiguous and load a flat vector.<o:p></o:p></p>
<p class="MsoNormal">You also mention that there is no documentation of x86_amx in the langref. I’d like to add x86_amx to the document. Is there any process to document for a type?<o:p></o:p></p>
<p class="MsoNormal"><sup><o:p> </o:p></sup></p>
<p class="MsoNormal"><img width="643" height="245" style="width:6.6944in;height:2.5486in" id="Picture_x0020_1" src="cid:image003.jpg@01D71C33.A3272380"><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks<o:p></o:p></p>
<p class="MsoNormal">Yuanke<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Florian Hahn <florian_hahn@apple.com> <br>
<b>Sent:</b> Thursday, March 18, 2021 6:03 PM<br>
<b>To:</b> Wang, Pengfei <pengfei.wang@intel.com><br>
<b>Cc:</b> llvm-dev <llvm-dev@lists.llvm.org>; Luo, Yuanke <yuanke.luo@intel.com><br>
<b>Subject:</b> Re: [llvm-dev] Does middle-end pass need to consider some special type when doing optimization? Or letting back-end to revert the optimization accordingly?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Mar 17, 2021, at 10:11, Wang, Pengfei via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi,<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">We are developing prototypes for Intel Advanced Matrix Extensions (AMX) [1] programing model in Clang and LLVM [2].<o:p></o:p></p>
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<p class="MsoNormal">We met several cases when the certain type we added are optimized unexpectedly in the middle-end. E.g. optimizing phi + biscast + load:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">From<o:p></o:p></p>
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<p class="MsoNormal">%a = load <256 x i32>, <256 x i32>* %mem, align 64<o:p></o:p></p>
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<p class="MsoNormal">… …<o:p></o:p></p>
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<p class="MsoNormal">%b = phi <256 x i32> [ %a, %label1 ], [%someother, %label2]<o:p></o:p></p>
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<p class="MsoNormal">%c = bitcast <256 x i32> %b to x86_amx<o:p></o:p></p>
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<p class="MsoNormal">To<o:p></o:p></p>
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<p class="MsoNormal">%a = bitcast <256 x i32>* %mem to x86_amx*<o:p></o:p></p>
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<p class="MsoNormal">%b = load x86_amx, x86_amx*, align 64<o:p></o:p></p>
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<p class="MsoNormal">… …<o:p></o:p></p>
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<p class="MsoNormal">%c = phi x86_amx [ %b, %label1 ], [%someother, %label2]<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">To prevent such unexpected transforms, we concretely added the type check in each point of the optimizations.<o:p></o:p></p>
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<p class="MsoNormal">Roman pointed out the changes are not the right direction [3], and thought it’s bug for backend. While we agreed backend might be able to handle it for the functionality, we think it is better to handle it in the midden-end since they are
negative optimizations for AMX.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">First, let me put some background here:<o:p></o:p></p>
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x86_amx* is different from trivial pointers.<o:p></o:p></li></ol>
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<p class="MsoNormal">The AMX load instruction is much different from other load instructions. It is not only need the memory address but also the shape / stride of the tile register. We did some extra work in the backend to deduce the shape information from
the context. We don’t want the pass to add new x86_amx related usage because this will result in the difficulty in deduction. That said bitcasting other pointer types to x86_amx* is not trivial as assumed here.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The problem appears to be that this difference is not modeled or specified in LLVM IR AFAICT. The current LangRef does not appear to specific `x86_amx` to start with. If pointers to `x86_amx` have different semantics than regular LLVM pointer
types, using regular LLVM pointer types for pointers to `x86_amx` may not be appropriate. I’ve not followed the previous AMX discussions closely, but it sounds like it may be good to reconsider how x86_amx pointers are modeled in LVM IR.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Also note that `bitcast` is specified as `no-op` (<a href="https://llvm.org/docs/LangRef.html#id293">https://llvm.org/docs/LangRef.html#id293</a>) (expect for pointers with different address spaces), but from what you mentioned above this
does not match the semantics for `x86_amx*`. It sounds like this is the underlying problem that should be addressed, because trying to update various middle end optimization tot ry to enforce the special semantics does not seem to be a scalable solution. <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">As Nuno mentioned, you could try and use a separate address space for `x86_amx` pointers to avoid pointer optimizations.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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The physical tile registers have more limitations. <o:p></o:p></li></ol>
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<li class="MsoListParagraph" style="margin-top:0in;margin-bottom:0in;mso-list:l1 level2 lfo2">
No copy instruction between tile registers.<o:p></o:p></li><li class="MsoListParagraph" style="margin-top:0in;margin-bottom:0in;mso-list:l1 level2 lfo2">
Spilling / reload a tile register is expensive in light of its size is 1024 bytes.<o:p></o:p></li><li class="MsoListParagraph" style="margin-top:0in;margin-bottom:0in;mso-list:l1 level2 lfo2">
The shapes of tile registers need to be pre-configured before use and all data in tile registers will turn into invalid once re-configured. That said we need to dominate as more tile registers as possible to configure their shapes with one configure instruction,
otherwise we need to spill and reload the live registers once we need to re-configure.<o:p></o:p></li><li class="MsoListParagraph" style="margin-top:0in;margin-bottom:0in;mso-list:l1 level2 lfo2">
The number of tile registers is rather small (only 8) and different shapes cannot be reused.<o:p></o:p></li></ol>
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<p class="MsoNormal">Based on the limitations, we need to reduce the use / live range of tile registers. But optimizations may increase the opportunity of the use. So even we can handle some combined operation for AMX type, we still prefer to prevent it from
the beginning. Unless we can totally roll back the optimization. Which is also not a good solution in my opinion.<o:p></o:p></p>
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<li class="MsoListParagraph" style="margin-top:0in;margin-bottom:0in;mso-list:l2 level1 lfo3">
For more information, please refer to discussion in [3].<o:p></o:p></li></ol>
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<p class="MsoNormal">For other optimization points, please refer [4][5].<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">I think the main controversy from Roman is if middle-end pass should consider some special type when doing optimization. I tend to let middle-end do the type check on account of the peculiarity of AMX type. But I’m not sure if we have precedent
to handle the similar issue in other targets. I’m open and glad to do it either way so long as we have an elegant solution.<o:p></o:p></p>
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<p class="MsoNormal">Any suggestions are welcome.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">IIUC the main problem is not that middle-end passes perform or not perform optimizations based on certain types. To me it sounds like the actual problem is that pointers to `x86_amx` do not behave like regular LLVM IR pointers and you are
trying to enforce extra restrictions for bit casts.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Cheers,<o:p></o:p></p>
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<p class="MsoNormal">Florian<o:p></o:p></p>
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