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Hi All! </div>
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<div>On behalf of Espressif Systems, I would like to propose Xtensa backend to be added as an experimental to LLVM project.</div>
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The new target should satisfy common rules (https://llvm.org/docs/DeveloperPolicy.html#adding-a-new-target) to be upstreamed in experimental mode.
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Therefore, we prepared an overview about conformance of the Xtensa backend to these rules:
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<div>1. Every target must have a code owner.</div>
<div> I added myself in CODE_OWNERS.txt as responsible for Xtensa backend support in the first patch.</div>
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<div>2. There must be an active community behind the target. </div>
<div> We have been developing the Xtensa backend project for 3 years, the latest version is ported to LLVM release 11.0.0.</div>
<div> <a href="https://github.com/espressif/llvm-project" target="_blank" rel="noopener noreferrer">
https://github.com/espressif/llvm-project</a> . The Xtensa backend project now implements object code generation, architecture-dependent optimizations and it became possible to use clang to compile software projects for the EPSP32 / ESP8266 processor family.</div>
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<div>3. The code must be free of contentious issues.</div>
<div> The Xtensa backend code deisgned with minimum changes in IR behaviour.</div>
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<div>4. The code conforms to all of the policies laid out in this developer policy document, including license, patent, and coding standards.</div>
<div> We paid attention to all these requirements in code design.</div>
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<div>5. The target should have either reasonable documentation on how it works (ISA, ABI, etc.) or a publicly available simulator/hardware (either free or cheap enough) - preferably both.</div>
<div> The Xtensa target is implemented in Qemu emulator https://github.com/qemu/qemu/tree/master/target/xtensa and has publicly available hardware implementations, for example ESP32/ESP8266 MCU's family https://www.espressif.com/en/products/socs/esp32 . We
also created the Xtensa ISA documentation project <a href="https://github.com/espressif/xtensa-isa-doc" target="_blank" rel="noopener noreferrer">
https://github.com/espressif/xtensa-isa-doc</a> , which is designed to simplify the patch review process, this project is based on public sources.</div>
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<div>Some time ago, we already presented this project for discussion to the LLVM community in a letter
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<div><a href="https://lists.llvm.org/pipermail/llvm-dev/2019-March/130796.html" target="_blank" rel="noopener noreferrer">https://lists.llvm.org/pipermail/llvm-dev/2019-March/130796.html</a> , and published a series of patches in the Phabricator:</div>
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<div>1. Recognize Xtensa in triple parsing code <a href="https://reviews.llvm.org/D64826" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64826</a> .<br>
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<div>2. Add Xtensa ELF definitions <a href="https://reviews.llvm.org/D64827" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64827</a> .<br>
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3. Initial version of the Xtensa backend <a href="https://reviews.llvm.org/D64829" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64829</a> .<br>
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4. Add basic * td files with Xtensa architecture description <a href="https://reviews.llvm.org/D64830" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64830</a> .<br>
<div>5. Add Xtensa MCTargetDescr initial functionality <a href="https://reviews.llvm.org/D64831" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64831</a> .<br>
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6. Add Xtensa basic assembler parser <a href="https://reviews.llvm.org/D64832" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64832</a> .<br>
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7. Add Xtensa instruction printer <a href="https://reviews.llvm.org/D64833" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64833</a> .<br>
<div>8. Add support of the Xtensa shift / load / store / move and processor control instructions.
<a href="https://reviews.llvm.org/D64834" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64834</a> .<br>
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9. Add basic support of Xtensa disassembler <a href="https://reviews.llvm.org/D64835" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64835</a> .<br>
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10. Add relaxations and fixups. Add rest part of Xtensa Core Instructions. <a href="https://reviews.llvm.org/D64836" target="_blank" rel="noopener noreferrer">
https://reviews.llvm.org/D64836</a> .<br>
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Currently, patches 1 and 3 have been approved, but other patches are still waiting for review. The patches 1-10 in the Phabricator are updated in accordance with the latest LLVM API changes and comments from the patches review.
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<div>Now exists a strong demand and interest from our large developer community for LLVM Xtensa backend and there are also some other companies in a world which have Xtensa based chips. For example, Xtensa backend helps to implement Rust for the Xtensa https://github.com/MabezDev/rust-xtensa
and TinyGo <a href="https://tinygo.org/faq/what-about-esp8266-esp32/" target="_blank" rel="noopener noreferrer">
https://tinygo.org/faq/what-about-esp8266-esp32/</a> .</div>
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<div>But for the further development of such projects, it would be much more convenient to have the Xtensa backend implementation in the main LLVM version.</div>
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<div>So, it would be great if the LLVM community could help resume the review process.</div>
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<div>All comments and suggestions are welcome!</div>
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Andrei Safronov</div>
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