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    <p>Thanks for highlighting that patch!</p>
    <p>Using instruction bundles indeed sounds interesting, as it seems
      more flexible. We'll see how far we get with this.</p>
    <p>Konstantin<br>
    </p>
    <div class="moz-cite-prefix">On 08.12.2020 16:10, Ryan Taylor wrote:<br>
    </div>
    <blockquote type="cite"
cite="mid:CABgVvXt_U4hfnqY1L5MdvgTTaXfNZAxw0_nZ9U+Sw6527Lnung@mail.gmail.com">
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        <div>We had a similar issue with a hardware bug where we changed
          the 32 bit branch instruction encoding into a 64 encoding, the
          other 32 bit being a NOP: <a
href="https://reviews.llvm.org/rG9ab812d4752b2a1442426db2ccc17dc95d12eb04"
            moz-do-not-send="true">https://reviews.llvm.org/rG9ab812d4752b2a1442426db2ccc17dc95d12eb04</a><br>
        </div>
        <div><br>
        </div>
        <div>We also looked at using a bundle instead of this encoding
          method as we thought that might have been cleaner but that's a
          bit more complex, not sure if either of these help you.</div>
        <div>
          <div><br>
            <div class="gmail_quote">
              <div dir="ltr" class="gmail_attr">On Tue, Dec 8, 2020 at
                9:47 AM Konstantin Schwarz via llvm-dev <<a
                  href="mailto:llvm-dev@lists.llvm.org"
                  moz-do-not-send="true">llvm-dev@lists.llvm.org</a>>
                wrote:<br>
              </div>
              <blockquote class="gmail_quote" style="margin:0px 0px 0px
                0.8ex;border-left:1px solid
                rgb(204,204,204);padding-left:1ex">
                <div>
                  <p>Hi Kai,<br>
                    <br>
                    did you make any progress on this topic?<br>
                    We have a similar case in our backend, where
                    conditional branches have only a limited range.<br>
                    So for hand-written assembly, we would like to relax
                    using the scheme you describe: invert the branch
                    condition and add an unconditional jump.<br>
                    <br>
                    As you've already discovered, the relaxInstruction
                    callback doesn't allow to insert additional
                    instructions, but requires the relaxed instruction
                    to be returned.<br>
                    We could work around that by relaxing to a pseudo
                    instruction whose size is the combined size of the
                    conditional branch + jump and expand it later to the
                    actual instructions, but that seems unnecessarily
                    complex.<br>
                    <br>
                    Did you come up with a better solution?<br>
                    <br>
                    Konstantin<br>
                  </p>
                  <div>On 07.10.2020 17:20, Philip Reames via llvm-dev
                    wrote:<br>
                  </div>
                  <blockquote type="cite">
                    <p>If done in the assembler, this is branch
                      relaxation.  You need to implement the calls backs
                      mayNeedRelaxation, and relaxInstruction on your
                      target MCAsmBackend.  The iteration relaxation
                      logic already exists, see the generic MC code.  <br>
                    </p>
                    <p>Philip<br>
                    </p>
                    <div>On 10/5/20 8:20 PM, Kai Wang via llvm-dev
                      wrote:<br>
                    </div>
                    <blockquote type="cite">
                      <div dir="ltr">
                        <div>Correct the title.</div>
                        <br>
                        <div class="gmail_quote">
                          <div dir="ltr" class="gmail_attr">On Tue, Oct
                            6, 2020 at 11:11 AM Kai Wang <<a
                              href="mailto:kai.wang@sifive.com"
                              target="_blank" moz-do-not-send="true">kai.wang@sifive.com</a>>
                            wrote:<br>
                          </div>
                          <blockquote class="gmail_quote"
                            style="margin:0px 0px 0px
                            0.8ex;border-left:1px solid
                            rgb(204,204,204);padding-left:1ex">
                            <div dir="ltr">
                              <div>Hi all,</div>
                              <div><br>
                              </div>
                              In RISC-V ISA, the range of conditional
                              branches is within 4KiB. In current
                              implementation, if the branch target is
                              out of range, LLVM MC will issue an error
                              message to tell users it could not resolve
                              the fixup record. I have compared the
                              result with the GNU assembler. GNU
                              assembler will convert the branch to
                              inverted one plus jump to make the branch
                              possible. The range of unconditional jump
                              is 1MiB. It looks like<br>
                              <br>
                              ##########################<br>
                              bne a0, a1, FAR_BRANCH<br>
                              …<br>
                              FAR_BRANCH:<br>
                              <br>
                              converted to
                              <div><br>
                                ##########################<br>
                                beq a0, a1, SKIP_J<br>
                                j FAR_BRANCH<br>
                                SKIP_J:<br>
                                …<br>
                                FAR_BRANCH:<br>
                                <br>
                                I found there is a target hook,
                                relaxInstruction, that tries to achieve
                                the similar goal. However, the target
                                hook only replaces one MCInst with
                                another one with a larger branch range.
                                For example, c.beqz will be converted to
                                beq in the RISC-V backend if the fixup
                                value is out of range. There seems no
                                target hook to convert one MCInst to a
                                complex pattern in LLVM MC. Do I miss
                                something obvious?<br>
                                <br>
                                I found there is a target hook,
                                finishLayout, to manipulate the code
                                generated. Does it make sense to
                                implement the feature in finishLayout?
                                Or is there any better idea to achieve
                                the conversion? Thanks a lot.<br>
                                <div><br>
                                </div>
                                <div>Best,</div>
                                <div>Kai</div>
                              </div>
                            </div>
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