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Hello list,</div>
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<span style="background-color:rgb(255, 255, 255);display:inline !important">The AArch64 Armv8.7-A LD64B/ST64B Accelerator extension<span> is ready to land [1]. </span></span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">The </span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">latest
Arm ACLE [2] introduces a data type for intrinsic support of the load/store instructions of this extension. </span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">The type is defined as </span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">`typedef
struct { uint64_t val[8]; } data512_t;` in §8.9 - Load/store 64 Byte intrinsics. </span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">We would like this type to be supported for inline assembly as well. </span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">The
basic problem is to determine what is the right type to represent this in LLVM IR and then what is the Machine Value type this maps to before we finally lower it to the GPR64x8 register class [3]. </span><span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">It has
to be a single data item, which means it must have a type that's 64 bytes / 512 bits large.</span></div>
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<span style="color: rgb(0, 0, 0); font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt;">An obvious choice is i512, but there is no Machine Value type for it. T<span style="background-color:rgb(255, 255, 255);display:inline !important">he integer
types<span> </span></span>in LLVM's enumeration of 'simple value types' only go up to i128, which means both i512 and i256 need to be added because most of the legalization / lowering machinery for integer types assumes that you can find an integer type half
the size. But can we legalize those types? The i256 value type doesn't even have a register class to begin with. Even if we manage to just legalize i512 for loads and stores it's not enough. Legitimate IR, which performs arithmetic on i512, would make the
compiler crash during instruction selection in the absence of i256.</span></div>
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Another idea was to use an array of [8 x i64], but this maps to MVT::Other which isn't specific enough to be dealt by the backend.</div>
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I think that it's not right to use any of the existing LLVM IR types, which leaves us with inventing a new one. Any thoughts on this?</div>
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Kind regards,</div>
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Alexandros</div>
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[1] <a href="https://reviews.llvm.org/D91775" id="LPlnk287911">https://reviews.llvm.org/D91775</a></div>
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[2] <a href="https://developer.arm.com/documentation/101028/latest" id="LPlnk">https://developer.arm.com/documentation/101028/latest</a></div>
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[3] <a href="https://reviews.llvm.org/D91774" id="LPlnk755539">https://reviews.llvm.org/D91774</a></div>
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