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<p>Hi Gabriel,</p>
<p>thank you so much for doing this! I'll try out the patch in our
downstream implementation right away. Do you know how big of an
impact this has on compile time compared to fast and greedy?</p>
<p>Cheers,</p>
<p>Dominik<br>
</p>
<div class="moz-cite-prefix">Am 28.10.20 um 14:32 schrieb Gabriel
Hjort Ċkerlund via llvm-dev:<br>
</div>
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<p class="MsoNormal"><span style="font-family:"Ericsson
Hilda",serif">Hi all,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Ericsson
Hilda",serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Ericsson
Hilda",serif" lang="EN-US">I have made an attempt of
implementing an optimal variant of the register bank
selector (regbankselect). The code is available for review
at <a href="https://reviews.llvm.org/D90304"
moz-do-not-send="true">https://reviews.llvm.org/D90304</a>,
and I would greatly appreciate if anyone interested can
provide their comments. I have run a few tests the
regbankselect-*.mir testcases for AAarch64 and it seems to
work, but more tests are surely needed to increase
confidence in the implementation. I also tried using AMDGPU,
but that backend does not provide the full list of
InstructionMappings for a given MachineInstr, which is
needed in order to compute the optimal selection of register
banks.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Ericsson
Hilda",serif" lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Ericsson
Hilda",serif" lang="EN-US">Cheers,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-family:"Ericsson
Hilda",serif" lang="EN-US">Gabriel Hjort Ċkerlund <o:p></o:p></span></p>
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