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<p class="MsoNormal"><span lang="EN-US">Thanks for prompt response, Andy</span></p>
<p class="MsoNormal"> </p>
<p class="MsoNormal"><span lang="EN-US">This will work for cases when address is not modified. However this doesn’t seem to work for pre/post increment load stores.</span></p>
<p class="MsoNormal"><span lang="EN-US">Consider data to address forwarding:</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">$x0 = ldr x0, [x1]</span></p>
<p class="MsoNormal"><span lang="EN-US">$x0, $x2 = ldr x2, [x0, 16]!</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">The second instruction will have it’s own latency for address modification ($x0 register). So I don’t see how we can use ReadAdr stuff</span></p>
<p class="MsoNormal"><span lang="EN-US">here. May be forwarding is not supposed to work in such cases for ARM cpus? Cortex-A55 software optimization guide says this:</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">“</span>load data from a limited set of load instructions can be forwarded from the beginning of the wr pipeline stage to either the load or store AGU base operand<span lang="EN-US">”</span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">However nothing is said about pre/post indexed forms.</span></p>
<p class="MsoNormal"> </p>
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<p class="MsoNormal" style="border:none; padding:0cm"><b>From: </b><a href="mailto:atrick@apple.com">Andrew Trick</a><br>
<b>Sent: </b>15 ñåíòÿáðÿ 2020 ã. 7:04<br>
<b>To: </b><a href="mailto:eleviant@accesssoftek.com">Evgeny Leviant</a><br>
<b>Cc: </b><a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br>
<b>Subject: </b>[EXTERNAL] Re: [llvm-dev] Simulation of load-store forwarding with MI scheduler on AArch64</p>
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<div class="">On Sep 14, 2020, at 9:40 AM, Evgeny Leviant via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div>
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<span lang="EN-US" class="">Hi list,</span></div>
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<span lang="EN-US" class=""> </span></div>
<div class="" style="margin:0cm; font-size:11pt; font-family:Calibri,sans-serif">
<span lang="EN-US" class="">Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64?</span></div>
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<span lang="EN-US" class="">For instance $x0 data latency in the example below should be 1 cycle</span></div>
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<span lang="EN-US" class=""> </span></div>
<div class="" style="margin:0cm; font-size:11pt; font-family:Calibri,sans-serif">
<span lang="EN-US" class="">ldr $x0, [$x1]</span></div>
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<span lang="EN-US" class="">str $x0, [$x2]</span></div>
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<span lang="EN-US" class=""> </span></div>
<div class="" style="margin:0cm; font-size:11pt; font-family:Calibri,sans-serif">
<span lang="EN-US" class="">But it should be 4 cycles if we have another instruction:</span></div>
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<span lang="EN-US" class=""> </span></div>
<div class="" style="margin:0cm; font-size:11pt; font-family:Calibri,sans-serif">
<span lang="EN-US" class="">ldr $x0, [$x1]</span></div>
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<span lang="EN-US" class="">add $x0, $x0, 4</span></div>
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<span lang="EN-US" class=""> </span></div>
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<span lang="EN-US" class="">For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how</span></div>
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<span lang="EN-US" class="">to do this with WriteLD or WriteST. Is there some workaround?</span></div>
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<div>The main purpose of ReadAdvance is pipeline forwarding.</div>
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<div>I think you can just want a read resource in your subtarget like this:</div>
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<div> def ReadAdr : SchedReadAdvance<3, [WriteLD]></div>
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<div>Briefly glancing at the AArch64 target I see this for stores:</div>
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<div> Sched<[WriteST]>;</div>
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<div>So it doesn't look like there's any existing name for the store’s address operand. You could add a general ReadAdr SchedRead resource</div>
<div>in AArch64Schedule.td. Then you would need to change the ReadAdr line in your subtarget to an override:</div>
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<div> def : ReadAdvance<ReadAdr, 3, [WriteLD]></div>
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<div>Or instead you can just add a rule in your subtarget listing the opcodes or using a regex, and using the ReadAdr resource that you defined in the same file.</div>
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<div> def : InstRW<[WriteST, ReadAdr], (instregex "ST(someregex)$")>;</div>
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<div>Being careful about store-pair and vector stores.</div>
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<div>Then you always want to debug your target’s llvm-tblgen command by adding a flag</div>
<div>-debug-only=subtarget-emitter</div>
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<div>And even trace the schedule for some simple cases with -debug-only=machine-scheduler</div>
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<div>I haven't actually done any of this in several years, someone with more recent experience may have better tips.</div>
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-Andy</div>
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