<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Sep 14, 2020, at 9:40 AM, Evgeny Leviant via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="WordSection1" style="page: WordSection1; caret-color: rgb(0, 0, 0); font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none;"><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">Hi list,<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64?<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">For instance $x0 data latency in the example below should be 1 cycle<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">ldr $x0, [$x1]<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">str $x0, [$x2]<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">But it should be 4 cycles if we have another instruction:<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">ldr $x0, [$x1]<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">add $x0, $x0, 4<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class=""><o:p class=""> </o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see how<o:p class=""></o:p></span></div><div style="margin: 0cm; font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span lang="EN-US" class="">to do this with WriteLD or WriteST. Is there some workaround?</span><o:p class=""></o:p></div></div></div></blockquote><br class=""></div><div><div>The main purpose of ReadAdvance is pipeline forwarding.</div><div><br class=""></div><div>I think you can just want a read resource in your subtarget like this:</div><div><br class=""></div><div> def ReadAdr : SchedReadAdvance<3, [WriteLD]></div><div><br class=""></div><div>Briefly glancing at the AArch64 target I see this for stores:</div><div><br class=""></div><div> Sched<[WriteST]>;</div><div><br class=""></div><div>So it doesn't look like there's any existing name for the store’s address operand. You could add a general ReadAdr SchedRead resource</div><div>in AArch64Schedule.td. Then you would need to change the ReadAdr line in your subtarget to an override:</div><div><br class=""></div><div> def : ReadAdvance<ReadAdr, 3, [WriteLD]></div><div><br class=""></div><div>Or instead you can just add a rule in your subtarget listing the opcodes or using a regex, and using the ReadAdr resource that you defined in the same file.</div><div><br class=""></div><div> def : InstRW<[WriteST, ReadAdr], (instregex "ST(someregex)$")>;</div><div><br class=""></div><div>Being careful about store-pair and vector stores.</div><div><br class=""></div><div>Then you always want to debug your target’s llvm-tblgen command by adding a flag</div><div>-debug-only=subtarget-emitter</div><div><br class=""></div><div>And even trace the schedule for some simple cases with -debug-only=machine-scheduler</div><div><br class=""></div><div>I haven't actually done any of this in several years, someone with more recent experience may have better tips.</div><div class=""><br class=""></div></div>-Andy</body></html>