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<div class="moz-cite-prefix">On 8/14/20 6:39 PM, Luo, Yuanke wrote:<br>
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<b><span lang="EN-US">From:</span></b><span lang="EN-US">
Hal Finkel <a class="moz-txt-link-rfc2396E" href="mailto:hfinkel@anl.gov"><hfinkel@anl.gov></a>
<br>
<b>Sent:</b> Friday, August 14, 2020 11:27 PM<br>
<b>To:</b> Luo, Yuanke <a class="moz-txt-link-rfc2396E" href="mailto:yuanke.luo@intel.com"><yuanke.luo@intel.com></a>;
<a class="moz-txt-link-abbreviated" href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>; <a class="moz-txt-link-abbreviated" href="mailto:florian_hahn@apple.com">florian_hahn@apple.com</a>; Kaylor,
Andrew <a class="moz-txt-link-rfc2396E" href="mailto:andrew.kaylor@intel.com"><andrew.kaylor@intel.com></a>; Topper, Craig
<a class="moz-txt-link-rfc2396E" href="mailto:craig.topper@intel.com"><craig.topper@intel.com></a>; Lu, Hongjiu
<a class="moz-txt-link-rfc2396E" href="mailto:hongjiu.lu@intel.com"><hongjiu.lu@intel.com></a><br>
<b>Subject:</b> Re: [llvm-dev] Intel AMX programming
model discussion.<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p><span lang="EN-US"><o:p> </o:p></span></p>
<div>
<p class="MsoNormal"><span lang="EN-US">On 8/14/20 8:27 AM,
Luo, Yuanke via llvm-dev wrote:<o:p></o:p></span></p>
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<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<p class="MsoNormal"><span lang="EN-US">Hi,<o:p></o:p></span></p>
...<span lang="EN-US"><o:p></o:p></span></blockquote>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
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style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0
level1 lfo2">
<!--[if !supportLists]--><span lang="EN-US"><span
style="mso-list:Ignore">8.<span style="font:7.0pt
"Times New Roman"">
</span></span></span><!--[endif]--><span lang="EN-US">Register
allocation<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">AMX register is
special. It needs to be configured before use and the
config instruction is expensive. To avoid unnecessary tile
configure, we collect the tile shape information as much
as possible and combine them into one ldtilecfg
instruction. The ldtilecfg instruction should dominate any
AMX instruction that access tile register. On the other
side, the ldtilecfg should post-dominated the instruction
that define the tile shape. For tile register spill, it
should avoid re-config due to the different tile shape,
the spilled register should be reloaded to the register
that share the same tile shape. Since tile register
allocation is special and it may allocate general virtual
register to configure tile register, we can add a sperate
pass to do it before general register allocation pass.
After register allocation, the tile shape information is
not needed anymore, so we can transform the pseudo AMX
instruction to real AMX instruction by removing the row
and column operands.<o:p></o:p></span></p>
</blockquote>
<p><span lang="EN-US"><o:p> </o:p></span></p>
<p><span lang="EN-US">Can you take advantage of our IPRA
capability so that internal function calls might avoid this
reconfiguration if the necessary configuration is always
done in the caller?<o:p></o:p></span></p>
<p><span lang="EN-US">[Yuanke] I don’t know IPRA capability and
I am very interesting on it. Would you post some linkage
that introduce IPRA?</span></p>
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<p><br>
</p>
<p>Interestingly, it looks like some documentation was written but
never committed: <a href="https://reviews.llvm.org/D23980">https://reviews.llvm.org/D23980</a>
- in general, if you search for IPRA in LLVM, you'll see the
relevant pieces. The really short description is that functions
are emitted in topological order, leaves of the call graph first,
so that customized clobber register masks can be attached to call
sites of relevant internal functions.<br>
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<p> -Hal</p>
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<p><span lang="EN-US"><o:p></o:p></span></p>
<p><span lang="EN-US">How will the implementation of
__builtin_setjmp/longjmp be affected?<o:p></o:p></span></p>
<p><span lang="EN-US">[Yuanke] That depends on the ABI. We
propose all tile register is caller saved, so I think
setjmp/longjmp is not affected.<o:p></o:p></span></p>
<p><span lang="EN-US">Thanks again,<o:p></o:p></span></p>
<p><span lang="EN-US">Hal<o:p></o:p></span></p>
<p><span lang="EN-US"><o:p> </o:p></span></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<p class="MsoListParagraph"
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level1 lfo2">
<!--[if !supportLists]--><span lang="EN-US"><span
style="mso-list:Ignore">9.<span style="font:7.0pt
"Times New Roman"">
</span></span></span><!--[endif]--><span lang="EN-US">Use
recommendation <o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Due to the shape
configure issue, we recommend user to define the tile
shape at the entry of the function entry and inline
function as much as possible. The AMX instructions focus
on computation instead of storage, so global variable for
tile data is not recommended.<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:10.5pt;line-height:105%" lang="EN-US"> </span><span
lang="EN-US"><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:10.5pt;line-height:105%" lang="EN-US">Thanks</span><span
lang="EN-US"><o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:10.5pt;line-height:105%" lang="EN-US">Yuanke</span><span
lang="EN-US"><o:p></o:p></span></p>
<p class="MsoNormal"
style="margin-bottom:0cm;margin-bottom:.0001pt;line-height:normal">
<span lang="EN-US"><br>
<br>
<o:p></o:p></span></p>
<pre><span lang="EN-US">_______________________________________________<o:p></o:p></span></pre>
<pre><span lang="EN-US">LLVM Developers mailing list<o:p></o:p></span></pre>
<pre><span lang="EN-US"><a href="mailto:llvm-dev@lists.llvm.org" moz-do-not-send="true">llvm-dev@lists.llvm.org</a><o:p></o:p></span></pre>
<pre><span lang="EN-US"><a href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" moz-do-not-send="true">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a><o:p></o:p></span></pre>
</blockquote>
<pre><span lang="EN-US">-- <o:p></o:p></span></pre>
<pre><span lang="EN-US">Hal Finkel<o:p></o:p></span></pre>
<pre><span lang="EN-US">Lead, Compiler Technology and Programming Languages<o:p></o:p></span></pre>
<pre><span lang="EN-US">Leadership Computing Facility<o:p></o:p></span></pre>
<pre><span lang="EN-US">Argonne National Laboratory<o:p></o:p></span></pre>
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<pre class="moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
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