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<p class="MsoNormal"><span lang="SV">Hello,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="SV"><o:p> </o:p></span></p>
<p class="MsoNormal">This is an RFC for adding intrinsics which perform saturating signed/unsigned left shift.<o:p></o:p></p>
<p class="MsoNormal">There is currently a patch on Phabricator here:<o:p></o:p></p>
<p class="MsoNormal"><a href="https://reviews.llvm.org/D83216">https://reviews.llvm.org/D83216</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The intrinsics are of the form<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span lang="SV"> i32 @llvm.sshl.sat.i32(i32, i32)<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="SV"> i32 @llvm.ushl.sat.i32(i32, i32)<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="SV"> <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="SV"> <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32>, <4 x i32>)<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="SV"><o:p> </o:p></span></p>
<p class="MsoNormal">and are overloaded with a single type which can be either an integer type or a vector of integers. The value(s) provided in the first operand are shifted left by the amount(s) given by the second operand. As with regular left shift instructions,
the second operand is an unsigned quantity and must be less than the integer bitwidth.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">If the true result of the operation (given infinite precision) lies outside of the maximum or minimum representable value of the signed/unsigned integer, the result saturates to the maximum or minimum depending on the sign of the shifted
value.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">These are useful for implementing the Embedded-C fixed-point arithmetic support in Clang, as previously detailed and discussed here:<o:p></o:p></p>
<p class="MsoNormal"><a href="http://lists.llvm.org/pipermail/llvm-dev/2018-August/125433.html">http://lists.llvm.org/pipermail/llvm-dev/2018-August/125433.html</a><o:p></o:p></p>
<p class="MsoNormal"><a href="http://lists.llvm.org/pipermail/cfe-dev/2018-May/058019.html">http://lists.llvm.org/pipermail/cfe-dev/2018-May/058019.html</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">It is of course possible to emit these shifts as regular IR instructions, but targets which support saturating shifts might have difficulties efficiently selecting native instructions if the optimizer undoes the particular expected instruction
pattern that the shifts would be selected on.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">/ Bevin<o:p></o:p></p>
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