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<div dir="ltr" data-setdir="false">Hello,</div><div dir="ltr" data-setdir="false"><br></div><div dir="ltr" data-setdir="false">Thank you for the information. I will look at the LLD source files you mention. Thank you also for the "veneer" name. I was aware of stubs, thunks and trampolines, not veneer. I will grep it on the LLVM code-base and see what I find.</div><div dir="ltr" data-setdir="false"><br></div><div dir="ltr" data-setdir="false">In the processor I'm working with, conditional jumps have a range of 1KB forward or backward. The range is problematic, as I'm currently unable to compile CoreMark for that processor (to be more precise, assembly generation works, but ELF object generation fails due to out-of-range conditional jumps). I'm afraid that many conditional jumps will be limited by their range. I therefore have to find a solution that limits the number of additional instructions, or jumps to linker-generated code, as much as possible.</div><div dir="ltr" data-setdir="false"><br></div><div dir="ltr" data-setdir="false">Thank you again. I now have information from which I hope to find a solution to my problem.</div><div dir="ltr" data-setdir="false"><br></div><div dir="ltr" data-setdir="false">Best regards,<br>Denis<br></div><div><br></div>
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Le mercredi 1 juillet 2020 à 12:10:41 UTC+2, Peter Smith <peter.smith@arm.com> a écrit :
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<div><div dir="ltr">Hello Denis,<br clear="none"><br clear="none">In Arm and AArch64 the limited range of immediates for branch instructions is addressed in two parts. The first is when there is a branch that is guaranteed to have a destination within the same section, in that case a 16-bit instruction is relaxed to a 32-bit one with a larger immediate. In Arm the range of the 32-bit instruction is considered large enough within a single section (-ffunction-sections may be needed for giant source files, not many single functions are larger than 16 megabytes). Branches that go across section boundaries and have relocations that the ABI says a linker must "veneer" are resolved at link time by redirecting to linker generated code (called many things from stub, thunk, veneer, trampoline ...) that completes the branch. There is support in LLD via Relocations.cpp, Thunks.cpp etc.<br clear="none"><br clear="none">Peter<br clear="none"><br clear="none">________________________________________<div class="yqt4546111656" id="yqtfd30249"><br clear="none">From: llvm-dev <<a shape="rect" ymailto="mailto:llvm-dev-bounces@lists.llvm.org" href="mailto:llvm-dev-bounces@lists.llvm.org">llvm-dev-bounces@lists.llvm.org</a>> on behalf of Denis Steckelmacher via llvm-dev <<a shape="rect" ymailto="mailto:llvm-dev@lists.llvm.org" href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br clear="none">Sent: 01 July 2020 09:47<br clear="none">To: <a shape="rect" ymailto="mailto:llvm-dev@lists.llvm.org" href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br clear="none">Subject: [llvm-dev] Handling far branches with fixups or ELF relocs<br clear="none"><br clear="none">Hello,<br clear="none"><br clear="none">I'm working on an LLVM backend for an experimental microprocessor. Work<br clear="none">is going on nicely, and I've until now found the answer to all my<br clear="none">questions directly in the LLVM source code, or in the documentation.<br clear="none"><br clear="none">However, I'm having problems with the AsmBackend class and the handling<br clear="none">of fixups.<br clear="none"><br clear="none">The processor I'm working with has a single conditional branch<br clear="none">instruction, JCC, that takes an IP-relative 9-bit immediate offset as<br clear="none">operand. A second version of the instruction takes a register as operand<br clear="none">and can therefore jump to any 32-bit address.<br clear="none"><br clear="none">In AsmBackend, there are methods for relaxing instructions, that I<br clear="none">wanted to use to replace "JCC imm9" instructions with a sequence of<br clear="none">instructions that jumps further. However, I have two questions:<br clear="none"><br clear="none">- relaxInstruction does not seem to be able to replace one instruction<br clear="none">with a sequence of instructions<br clear="none">- I've looked at many other LLVM backends (AVR, ARC, ARM, MIPS and<br clear="none">RISC-V), and none of them really seem to do interesting things in<br clear="none">relaxInstruction. ARM for instance relaxes Thumb instructions to normal<br clear="none">instructions, and RISC-V relaxes compressed instructions to normal ones<br clear="none">too. But in both cases, even the normal instructions have limited range,<br clear="none">for which there is an assertion, but no "solution" for when a branch<br clear="none">exceeds the range of the instruction.<br clear="none"><br clear="none">It therefore seems that the problem of "conditional branches that jump<br clear="none">too far" is solved elsewhere, but I could not find that location. I<br clear="none">looked at LLD, and I've seen that RISC-V has some code there (related to<br clear="none">the PLT) that produces sequences of instructions, but not the other targets.<br clear="none"><br clear="none">So, what would be the best way to change "JCC imm9" instructions to<br clear="none">something else when a branch has to jump further than 256 instructions<br clear="none">before or after the current one?<br clear="none"><br clear="none">Best regards,<br clear="none">Denis Steckelmacher</div><br clear="none">_______________________________________________<br clear="none">LLVM Developers mailing list<br clear="none"><a shape="rect" ymailto="mailto:llvm-dev@lists.llvm.org" href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br clear="none"><a shape="rect" href="https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev" target="_blank">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev</a></div></div>
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