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<p class="msipheader4d0fcdd7" align="Left" style="margin:0"><span style="font-size:10.0pt;font-family:Arial;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span></p>
<br>
<div class="WordSection1">
<p class="MsoNormal">Hi All,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">For the AMDGPU architecture, during RA, we prefer to have a cost associated with the registers (CostPerUse) based on a target entity (for instance, the Calling Convention of the current MachineFunction).<o:p></o:p></p>
<p class="MsoNormal">Presently CostPerUse is a one-time static value (either zero or a positive value) generated through table-gen.<o:p></o:p></p>
<p class="MsoNormal">The current implementation doesn’t allow us to control the reg-cost on the fly.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The AMDGPU ABI has recently been revised by introducing more caller-saved VGPRs (the exact details are explained towards the end of this e-mail), and found that having a dynamic register cost is important to achieve an optical allocation.
<o:p></o:p></p>
<p class="MsoNormal">Precisely, it is important to limit the number of VGPRs allocated for a kernel/device-function to a smallest value since it will have a direct impact on the occupancy. The occupancy means the number of wavefronts that can be launched at
runtime for a kernel program.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Some initial thoughts on how to fix it:<o:p></o:p></p>
<ol style="margin-top:0in" start="1" type="1">
<li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">Have a target interface (a switch) to enable/discard the CostPerUse value.<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">Get the register cost in the same way we define various calling conventions (*CallingConv.td).<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">Compute the CostPerUse in the way the AllocationOrder for the registers is determined during RA.<o:p></o:p></li></ol>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The first one is the easiest method and that solves the immediate problem we currently address.<o:p></o:p></p>
<p class="MsoNormal">However, the other two options are better if we want to associate different reg-cost values for different calling conventions (I presume, it will arise at some point).
<o:p></o:p></p>
<p class="MsoNormal">Other than these options, there can be a better way to fix it. Any suggestion in this regard would be helpful.
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">AMDGPU ABI changes and the motivation for this discussion:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Before the new ABI change:<o:p></o:p></p>
<p class="MsoNormal" style="text-indent:.5in">Apart from the initial reserved 32 argument registers, all VGPRs are callee-saved registers (VGPR32 - VGPR255).<o:p></o:p></p>
<p class="MsoNormal">With the new ABI:<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:.5in">We made VGPR32 - VGPR255 into equal number of callee-saved and caller-saved registers.<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:.5in">For the same occupancy reason, these two sets are interleaved at a split boundary of 8.<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.0in">VGPR32-VGPR39 (Caller-saved)<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.0in">VGPR40-VGPR47 (Callee-saved)<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.0in">VGPR48-VGPR55 (Caller-saved)<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.0in"> -<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.0in"> -<o:p></o:p></p>
<p class="MsoNormal" style="margin-left:1.0in">VGPR248-VGPR255 (Callee-saved)<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">With the new ABI, the allocator’s preference for callee-saved vs caller-saved depends on the input program.
<o:p></o:p></p>
<p class="MsoNormal">RA may end up allocating more caller-saved registers than the callee-saved in certain cases. The other way of allocation is possible too (more callee-saved registers)<o:p></o:p></p>
<p class="MsoNormal">In either case, there will be unallocated registers left behind, bumping up the final VGPRs into a considerable number. It will have a bad impact on the occupancy.<o:p></o:p></p>
<p class="MsoNormal">To override the default allocation preferences of RA, we tried to set a cost for all VGPRs such that the higher indices will have higher cost.
<o:p></o:p></p>
<p class="MsoNormal">It eliminated the problem by allocating all lower registers before picking the higher one, and with an expense of some spills in certain cases which is acceptable.
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">But for the kernels with no device-function calls, the register cost is unnecessary. Because there is no ABI for such kernel programs.<o:p></o:p></p>
<p class="MsoNormal">It caused a performance penalty for such kernels due to the register cost.<o:p></o:p></p>
<p class="MsoNormal">That’s the exact reason we need a method to determine dynamically either to have a reg-cost or not to have one.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Christudasan<o:p></o:p></p>
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