<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sun, May 10, 2020 at 5:59 PM Andrea Di Biagio <<a href="mailto:andrea.dibiagio@gmail.com">andrea.dibiagio@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div dir="ltr"><div>Hi Alex,</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sun, May 10, 2020 at 4:00 PM Alex Renda <<a href="mailto:renda@csail.mit.edu" target="_blank">renda@csail.mit.edu</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div>
<div name="messageBodySection">
<div dir="auto">Thanks, that’s very helpful!<br>
<br>
<br>
<br>
Also, sorry for the miscue on that bug with the 2/4 cycles — I realize now that that’s an artifact of a change that I made to not crash when resource groups overlap without all atomic subunits being specified:<br>
<br>
`echo 'fxrstor (%rsp)' | llvm-mca -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=haswell`<br>
crashes (because fxrstor requests `HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156`, so HWPort0156 ends up asserting because 0,1,5, and 6 are all taken), so I added:<br>
```<br>
--- a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp<br>
+++ b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp<br>
@@ -292,7 +292,7 @@ void ResourceManager::issueInstruction(<br>
ResourceState &RS = *Resources[Index];<br>
<br>
- if (!R.second.isReserved()) {<br>
+ if (!R.second.isReserved() && RS.isReady()) {<br>
ResourceRef Pipe = selectPipe(R.first);<br>
use(Pipe);<br>
BusyResources[Pipe] += CS.size();<br>
```<br>
which is probably the cause of that weird behavior I reported.<br>
<br>
<br>
<br>
I’m also somewhat curious about what “NumUnits” is modeling: I haven’t totally worked through the code yet, but it seems that when more (not necessarily atomic) sub-resources of a resource group are requested, more “NumUnits” of that group is requested. This doesn’t seem particularly intuitive to me, at least in my mental model of Haswell scheduling (and also leads to some infinite loops like `echo ‘fldenv (%rsp)' | llvm-mca -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=haswell`, which requests HWPort0,HWPort1,HWPort01,HWPort05, and HWPort015, meaning that HWPort015 never schedules because it requests 4 “NumUnits” but only 3 are ever available). Is there some particular behavior that this is modeling?<br></div></div></div></blockquote><div><br></div><div>
<div>The issue with
fxrstor is unfortunately a bug. I'll see if I can fix it.<br></div><div><br>Strictly speaking, that "NumUnits" quantity is literally the number of processor resource units consumed. By construction, it should never exceed the actual number of resource units declared by a processor resource in the scheduling model (i.e. this particular field of MCProcResourceDesc - <a href="https://llvm.org/doxygen/structllvm_1_1MCProcResourceDesc.html#a9d4d0cc34fcce4779dc4445d8265fffc" target="_blank">https://llvm.org/doxygen/structllvm_1_1MCProcResourceDesc.html#a9d4d0cc34fcce4779dc4445d8265fffc</a>).<br><br>
</div><div>The reason why you see the crash/assert is because the number of resource units for scheduler resources is incorrectly set for that instruction by the instruction builder in llvm-mca (
lib/MCA/InstrBuilder.cpp
- function `initializeUsedResources()`). I am looking at it.<br></div></div></div></div></blockquote><div><br></div><div>Hi Alex,<br><br></div><div>This issue should be fixed by commit
47b95d7cf462.<br></div><div>I now understand why so many questions about the meaning of reserved resources :-).<br></div><div>Could you please check if that commit fixes the issue for you too?<br></div><div><br></div><div>As Andy wrote, in the future we should really look into adding an optional DelayCycles vector for SchedWriteRes.<br></div><div>That would be the ideal improvement; it would also allow us to get rid of the "reserved" bit.<br><br></div><div>Thanks,<br></div><div>-Andrea<br></div><div> <br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div class="gmail_quote"><div><div><br></div><div>About what Andy suggested: I really like the idea of having a vector of delay-cycles for consumed resources. It would fix most of these problems in Haswell, and it could be used to improve the description of some instructions on other processor models too. I agree that it should not be difficult to implement (at least, the tablegen part should be pretty mechanical); the resource allocation logic in class ResourceManager (in llvm-mca) would require a bit of refactoring. Other than that, the rest should be doable.<br><br></div><div>-Andrea<br></div><div> </div></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div><div name="messageBodySection"><div dir="auto"></div>
</div>
<div name="messageSignatureSection"><br>
<div dir="auto">-Alex</div>
</div>
<div name="messageReplySection">On May 10, 2020, 9:32 AM -0400, Andrew Trick <<a href="mailto:atrick@apple.com" target="_blank">atrick@apple.com</a>>, wrote:<br>
<blockquote type="cite" style="border-left:thin solid grey;margin:5px;padding-left:10px"><br>
<div><br>
<blockquote type="cite">
<div>On May 9, 2020, at 5:12 PM, Andrea Di Biagio via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:</div>
<br>
<div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none">The llvm scheduling model is quite simple and doesn't allow mca to accurately simulate the execution of individual uOPs. That limitation is sort-of acceptable if you consider how the scheduling model framework was originally designed with a different goal in mind (i.e. machine scheduling). The lack of expressiveness of the llvm scheduling model unfortunately limits the accuracy of llvm-mca: we know the number of uOPs of an instruction. However we don't know which resources are consumed by which micro-opcodes. So we cannot accurately simulate the independent execution of individual opcodes of an instruction.<br>
<br>
Another "problem" is that it is not possible to describe when uOPs effectively start consuming resources. At the moment, the expectation is that resource consumption always starts at relative cycle #0 (relative to the instruction issue cycle).<br>
Example: an horizontal add on x86 is usually decoded into a pair of shuffles uOPs and a single (data-dependent) vector ADD uOP.<br></div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none">The ADD uOP doesn't execute immediately because it needs to wait for the other two shuffle uOPs. It means that the ALU pipe is still available at relative cycle #0 and it is only consumed starting from relative cycle #1 (ssuming that both shuffles can start execution at relative cycle #0). In practice, the llvm scheduling model only allows us to declare which pipeline resources are consumed, and for how long (in number cycles). So we cannot accurately describe to mca that the delayed consumption of the ALU pipe.<br></div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none">Now think about what happens if: the first shuffle uOP consumes 1cy of HWPort0, and the second shuffle uOp consumes 1cy of HWPort1, and the ADD consumes 1cy of HWPort01. We end up in that "odd" situation you described where HWPort01 is "reserved" for 1cy.<br></div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none">In reality, that 1cy of HWPort01 should have started 1cy after the other two opcodes. At that point, both pipelines would have been seen available.<br></div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none"><br>
In conclusion, the presence of a "reserved" flag is not ideal, but it is sort-of a consequence of the above mentioned two limitations (plus the way how the Haswell and Broadwell models were originally designed).<br>
<br></div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none">I hope it helps,<br></div>
<div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant-caps:normal;font-weight:normal;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;text-decoration:none">-Andrea</div>
</div>
</blockquote>
</div>
<br>
<div>
<div>Food for thought...</div>
<div><br></div>
<div>It would be easy to add a DelayCycles vector to SchedWriteRes to indicate the relative start cycle for each reserved resource. That would effectively model dependent uOps.</div>
<div><br></div>
<div>NumMicroOps is only meant to model any general limitation of the cpu frontend to issue/rename/retire micro-ops. So, yes, there's no way to associate resources with specific uOps. You can mark any kind of resource as "dynamically scheduled" (BufferSize = -1). If an instruction uses different kinds of dynamic resources, then those need not be reserved at the same time. If we had the DelayCycles vector, it could be interpreted as "this resource must be reserved N cycles after prior reservations of other resources".</div>
</div>
<div><br></div>
<div>-Andy</div>
</blockquote>
</div>
</div>
</blockquote></div></div>
</blockquote></div></div>