<div dir="ltr"><b>The problem is, I have an instruction named LQP, which load 4x32-bit from memory and store them into 4 consecutive GPRs, such as, LQP a0, a4, a5, 4,</b><div><b> the loaded data will be stored in (a3,a2,a1,a0), the data address is 4(a4+a5).</b><div><br></div><div><b>The RISC-V inline assembly like this:</b></div><div><b><br></b></div><div><font color="#ff0000"> asm volatile</font><br> (<br> "lqp %[z], %[x], %[y], 4\n\t"<br> : [z] "=r" (c)<br> : [x] "r" (a), [y] "r" (b)<br> ) ;<br></div><div><br></div><div><b>To get this done, I creat to GPR groups and change the LQP instruction's definition, like this:</b></div><div><br></div><div><font color="#ff0000">def GPRA0</font> : RegisterClass<"RISCV", [XLenVT], 32, (add X10)> {<br> let RegInfos = RegInfoByHwMode<<br> [RV32, RV64, DefaultMode],<br> [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;<br>}<br></div><div><br></div><div>def GPRNOA0A1A2A3 : RegisterClass<"RISCV", [XLenVT], 32, (add<br> (sequence "X%u", 14, 17),<br> (sequence "X%u", 5, 7),<br> (sequence "X%u", 28, 31),<br> (sequence "X%u", 8, 9),<br> (sequence "X%u", 18, 27),<br> (sequence "X%u", 0, 4)<br> )> {<br> let RegInfos = RegInfoByHwMode<<br> [RV32, RV64, DefaultMode],<br> [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;<br>}<br></div><div><br></div><div>let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in<br><font color="#ff0000">def LQP</font> : RVInstRI<0b11, 0b000, OPC_HX_CUS0, <br> (outs GPRA0:$rd), (ins GPRNOA0A1A2A3:$rs1, GPRNOA0A1A2A3:$rs2, simm5:$shift),<br> "lqp", "$rd, $rs1, $rs2, $shift">, Sched<[]> {<br> bits<5> shift;<br> bits<5> rs1;<br> bits<5> rs2;<br> bits<5> rd;<br><br> let Inst{31-30} = 0b11;<br> let Inst{29-25} = shift;<br> let Inst{24-20} = rs2;<br> let Inst{19-15} = rs1;<br> let Inst{14-12} = 0b000;<br> let Inst{11-7} = rd;<br> let Opcode = OPC_HX_CUS0.Value;<br>}<br></div><div><br></div><div><b>and the
DecodeStatus as well, </b></div><div><br></div><div><font color="#ff0000">static DecodeStatus</font> DecodeGPRA0RegisterClass(MCInst &Inst, uint64_t RegNo,<br> uint64_t Address,<br> const void *Decoder) {<br> if (RegNo != 10) {<br> return MCDisassembler::Fail;<br> }<br><br> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);<br>}<br></div><div><br></div><div>static DecodeStatus DecodeGPRNOA0A1A2A3RegisterClass(MCInst &Inst, uint64_t RegNo,<br> uint64_t Address,<br> const void *Decoder) {<br> if (RegNo == 10 || RegNo == 11 || RegNo == 12 || RegNo == 13) {<br> return MCDisassembler::Fail;<br> }<br><br> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);<br>}<br><br><font color="#ff0000">static DecodeStatus DecodeGPRNOA0A1RegisterClass</font>(MCInst &Inst, uint64_t RegNo,<br> uint64_t Address,<br> const void *Decoder) {<br> if (RegNo == 10 || RegNo == 11) {<br> return MCDisassembler::Fail;<br> }<br><br> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);<br>}<br></div><div><br></div></div><div><b>Rebuild LLVM+clang, and compile the above c code which got such an error:</b></div><div><br></div><div><font color="#ff0000">clang</font> -I./env -I./common -I./src/test_newinst -I/home/llvm/workspace/llvm/llvm-project/llvm_install/riscv32-unknown-elf/include -mcmodel=medany -static -std=gnu99 -fno-common -fno-builtin-printf -march=rv32imac -mabi=ilp32 -DMB_ADDR=0x11ffC -O3 --target=riscv32-unknown-elf --sysroot=/home/llvm/workspace/riscv/riscv-tc-20200316/bin/riscv32-unknown-elf --gcc-toolchain=/home/llvm/workspace/riscv/riscv-tc-20200316 -o ./build/test_newinst/test_newinst ./src/test_newinst/main.c ./common/syscalls.c ./common/dev.c ./common/crt.S -static -nostartfiles -lm -lgcc -T ./common/test.ld<br><br>./src/test_newinst/main.c:117:5: <font color="#ff0000">error: invalid operand for instruction</font><br> "lqp %[z], %[x], %[y], 4\n\t"<br> ^<br> <br><inline asm>:1:8: note: instantiated into assembly here<br> lqp a2, a0, a1, 4<br></div><div><br></div><div><b>This error is obvious, and due to the Match_InvalidOperand, I wonder why the changes do not make any effect for LQP instruction.</b></div><div><b>And I have checked the OperandInfo111[] and RISCVInsts[] for the LQP instruction, </b></div><div><br></div><div><font color="#ff0000">static const MCOperandInfo OperandInfo111</font>[] = { { RISCV::GPRA0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNOA0A1A2A3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNOA0A1A2A3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM5, 0 }, };<br><br>{ 457, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x12ULL, nullptr, nullptr, <font color="#ff0000">OperandInfo111</font>, -1 ,nullptr }, // <font color="#ff0000">Inst #457 = LQP</font><br></div><div><br></div><div><b>Do I miss something or what I can do in this situation?</b></div><div><br></div></div>