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<p class="MsoNormal">Below is the performance and code size ratio of SPEC2017. <o:p>
</o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Table 1 shows the observed performance impact of the MCU on the specint2017 and specfp2017 benchmark suite when compiled with LLVM compiler. The columns labeled HW show that there is ~2% performance loss as measured by the geomean. Performance
loss on individual components was observed to be as high as 7%.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Software-based tools to mitigate these effects are being developed and are outlined below. From our experiments, recompiling the benchmarks recovered the geomean performance to within 99% of the originally observed performance, and the
maximum performance loss in SPEC benchmarks was subsequently reduced to within 4% of the original performance.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">We also measured the increase in code size due to the addition of padding to instructions to align branches correctly (Table 2). The geomean increase in code size is 2-3% with individual outliers of up to 4%.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Table 1 - SPEC2017 SW/HW mitigation vs. baseline performance ratio:<o:p></o:p></p>
<p class="MsoNormal">test SW vs baseline HW vs baseline HW+SW vs baseline<o:p></o:p></p>
<p class="MsoNormal">500.perlbench_r 0.97 0.97 0.96<o:p></o:p></p>
<p class="MsoNormal">502.gcc_r 1.00 0.99 0.99<o:p></o:p></p>
<p class="MsoNormal">505.mcf_r 1.00 0.97 1.01<o:p></o:p></p>
<p class="MsoNormal">520.omnetpp_r 1.00 0.99 0.99<o:p></o:p></p>
<p class="MsoNormal">523.xalancbmk_r 0.99 0.99 0.99<o:p></o:p></p>
<p class="MsoNormal">525.x264_r 1.00 0.96 0.99<o:p></o:p></p>
<p class="MsoNormal">531.deepsjeng_r 1.00 0.98 0.99<o:p></o:p></p>
<p class="MsoNormal">541.leela_r 1.00 1.00 1.00<o:p></o:p></p>
<p class="MsoNormal">557.xz_r 1.02 0.95 1.02<o:p></o:p></p>
<p class="MsoNormal">SIR 1.00 0.98 0.99<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">508.namd_r 1.00 0.99 1.00<o:p></o:p></p>
<p class="MsoNormal">510.parest_r 1.00 1.00 1.01<o:p></o:p></p>
<p class="MsoNormal">511.povray_r 1.02 0.96 1.02<o:p></o:p></p>
<p class="MsoNormal">519.lbm_r 1.00 1.01 1.00<o:p></o:p></p>
<p class="MsoNormal">526.blender_r 0.99 0.93 1.00<o:p></o:p></p>
<p class="MsoNormal">538.imagick_r 0.99 0.99 1.00<o:p></o:p></p>
<p class="MsoNormal">544.nab_r 1.00 0.98 1.00<o:p></o:p></p>
<p class="MsoNormal">FIR 1.00 0.98 1.00<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Table 2 - SPEC2017 SW/HW mitigation vs. baseline Code Size ratio:<o:p></o:p></p>
<p class="MsoNormal">test baseline SW<o:p></o:p></p>
<p class="MsoNormal">500.perlbench_r 1 1.04<o:p></o:p></p>
<p class="MsoNormal">502.gcc_r 1 1.04<o:p></o:p></p>
<p class="MsoNormal">505.mcf_r 1 1.02<o:p></o:p></p>
<p class="MsoNormal">520.omnetpp_r 1 1.04<o:p></o:p></p>
<p class="MsoNormal">523.xalancbmk_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">525.x264_r 1 1.02<o:p></o:p></p>
<p class="MsoNormal">531.deepsjeng_r 1 1.02<o:p></o:p></p>
<p class="MsoNormal">541.leela_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">557.xz_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">SIR Geomean 1 1.03<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">508.namd_r 1 1.01<o:p></o:p></p>
<p class="MsoNormal">510.parest_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">511.povray_r 1 1.02<o:p></o:p></p>
<p class="MsoNormal">519.lbm_r 1 1.01<o:p></o:p></p>
<p class="MsoNormal">526.blender_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">538.imagick_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">544.nab_r 1 1.03<o:p></o:p></p>
<p class="MsoNormal">SFR Geomean 1 1.02<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Test date:<o:p></o:p></p>
<p class="MsoNormal"> 2019/11/10<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">System Configuration:<o:p></o:p></p>
<p class="MsoNormal">OS: Red Hat* 8.0 x86_64<o:p></o:p></p>
<p class="MsoNormal">Memory: 191 GB<o:p></o:p></p>
<p class="MsoNormal">CPUCount: 2<o:p></o:p></p>
<p class="MsoNormal">CoreCount: 40<o:p></o:p></p>
<p class="MsoNormal">Intel HyperThreading: yes<o:p></o:p></p>
<p class="MsoNormal">CPU Model: Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz<o:p></o:p></p>
<p class="MsoNormal">Microcode w/o hw mitigation: 0x200005e<o:p></o:p></p>
<p class="MsoNormal">Microcode with hw mitigation: 0x2000063<o:p></o:p></p>
<p class="MsoNormal">Compiler options: <o:p></o:p></p>
<p class="MsoNormal">unmitigated: -march=skylake-avx512 -mfpmath=sse -Ofast -funroll-loops –flto<o:p></o:p></p>
<p class="MsoNormal">mitigated: -march=skylake-avx512 -mfpmath=sse -Ofast -funroll-loops –flto -Wl,-plugin-opt=-x86-branches-within-32B-boundaries<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"> 1. Baseline means the system w/o MCU mitigation and w/o SW mitigation.<o:p></o:p></p>
<p class="MsoNormal"> 2. SW means prefix mitigation is applied to a Non MCU system.<o:p></o:p></p>
<p class="MsoNormal"> 3. HW means the MCU mitigation is applied w/o SW mitigation.<o:p></o:p></p>
<p class="MsoNormal"> 4. HW+SW means both MCU and prefix mitigations are applied.<o:p></o:p></p>
<p class="MsoNormal"> 5. LLVM measurements are only limited to C/C++ benchmarks. All Fortran benchmarks are excluded.<o:p></o:p></p>
<p class="MsoNormal"> 6. The test is done on an engineering build plus the SW mitigation patch. It may be variant from build to build.
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">##Disclaimer:<o:p></o:p></p>
<p class="MsoNormal">For more complete information about performance and benchmark results, visit www.intel.com/benchmarks<http://www.intel.com/benchmarks>. For specific information and notices/disclaimers regarding the Jump Conditional Code Erratum, visit
https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf.<o:p></o:p></p>
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