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<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">Thank you! <o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">I took a look at this method (</span><span lang="EN-US" style="font-size:11.0pt">ARMBaseInstrInfo::optimizeCompareInstr</span><span lang="EN-US" style="color:#1F497D">) and how it is used.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">So,if I understood correctly, I need to add new method to TargetInstrInfo (similar to
</span><span lang="EN-US" style="font-size:11.0pt">optimizeCompareInstr</span><span lang="EN-US" style="color:#1F497D"> - e.g. optimizeAddInstr) and implement it in AArch64InstrInfo.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">This method should be able to transform code like this:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:18.0pt"><span lang="EN-US" style="color:#1F497D">%47:gpr64 = ANDXrr %46:gpr64, %32:gpr64<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:18.0pt"><span lang="EN-US" style="color:#1F497D">%48:gpr64common = ORRXrr killed %47:gpr64, %28:gpr64common<o:p></o:p></span></p>
<p class="MsoListParagraph" style="margin-left:18.0pt;text-indent:0cm"><span lang="EN-US" style="color:#1F497D">%49:gpr64 = ANDSXrr %46:gpr64, %32:gpr64, implicit-def $nzcv<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">to this form:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US" style="color:#1F497D">%47:gpr64 = ANDSXrr %46:gpr64, %32:gpr64, implicit-def $nzcv<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US" style="color:#1F497D">%48:gpr64common = ORRXrr killed %47:gpr64, %28:gpr64common<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">Is everything correct?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><b><span lang="EN-US" style="font-size:11.0pt">From:</span></b><span lang="EN-US" style="font-size:11.0pt"> Eli Friedman [mailto:efriedma@quicinc.com]
<br>
<b>Sent:</b> Friday, November 22, 2019 9:53 PM<br>
<b>To:</b> Kosov Pavel <kosov.pavel@huawei.com>; LLVM Dev <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> RE: [llvm-dev] [ARM] Peephole optimization ( instructions tst + add )<o:p></o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">You probably want to do this some time before register allocation, so you don’t have to worry about physical register definitions.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">Maybe take a look at what ARM does in ARMBaseInstrInfo::optimizeCompareInstr ?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">-Eli<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><b><span lang="EN-US" style="font-size:11.0pt">From:</span></b><span lang="EN-US" style="font-size:11.0pt"> Kosov Pavel <</span><span lang="EN-US"><a href="mailto:kosov.pavel@huawei.com"><span style="font-size:11.0pt">kosov.pavel@huawei.com</span></a></span><span lang="EN-US" style="font-size:11.0pt">>
<br>
<b>Sent:</b> Friday, November 22, 2019 3:09 AM<br>
<b>To:</b> Eli Friedman <</span><span lang="EN-US"><a href="mailto:efriedma@quicinc.com"><span style="font-size:11.0pt">efriedma@quicinc.com</span></a></span><span lang="EN-US" style="font-size:11.0pt">>; LLVM Dev <</span><span lang="EN-US"><a href="mailto:llvm-dev@lists.llvm.org"><span style="font-size:11.0pt">llvm-dev@lists.llvm.org</span></a></span><span lang="EN-US" style="font-size:11.0pt">><br>
<b>Subject:</b> [EXT] RE: [llvm-dev] [ARM] Peephole optimization ( instructions tst + add )<o:p></o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">Ok, thank you, I will implement it then.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D">As far as I see this optimization should be done in AArch64LoadStoreOptimizer, is it right?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><b><span lang="EN-US" style="font-size:11.0pt">From:</span></b><span lang="EN-US" style="font-size:11.0pt"> Eli Friedman [</span><span lang="EN-US"><a href="mailto:efriedma@quicinc.com"><span style="font-size:11.0pt">mailto:efriedma@quicinc.com</span></a></span><span lang="EN-US" style="font-size:11.0pt">]
<br>
<b>Sent:</b> Thursday, November 21, 2019 11:55 PM<br>
<b>To:</b> Kosov Pavel <</span><span lang="EN-US"><a href="mailto:kosov.pavel@huawei.com"><span style="font-size:11.0pt">kosov.pavel@huawei.com</span></a></span><span lang="EN-US" style="font-size:11.0pt">>; LLVM Dev <</span><span lang="EN-US"><a href="mailto:llvm-dev@lists.llvm.org"><span style="font-size:11.0pt">llvm-dev@lists.llvm.org</span></a></span><span lang="EN-US" style="font-size:11.0pt">><br>
<b>Subject:</b> RE: [llvm-dev] [ARM] Peephole optimization ( instructions tst + add )<o:p></o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">That transform is legal; it’s a missed optimization.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">-Eli<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt"><o:p> </o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><b><span lang="EN-US" style="font-size:11.0pt">From:</span></b><span lang="EN-US" style="font-size:11.0pt"> llvm-dev <</span><span lang="EN-US"><a href="mailto:llvm-dev-bounces@lists.llvm.org"><span style="font-size:11.0pt">llvm-dev-bounces@lists.llvm.org</span></a></span><span lang="EN-US" style="font-size:11.0pt">>
<b>On Behalf Of </b>Kosov Pavel via llvm-dev<br>
<b>Sent:</b> Thursday, November 21, 2019 2:00 AM<br>
<b>To:</b> </span><span lang="EN-US"><a href="mailto:llvm-dev@lists.llvm.org"><span style="font-size:11.0pt">llvm-dev@lists.llvm.org</span></a></span><span lang="EN-US" style="font-size:11.0pt"><br>
<b>Subject:</b> [EXT] [llvm-dev] [ARM] Peephole optimization ( instructions tst + add )<o:p></o:p></span></p>
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<p class="MsoNormal" align="left" style="text-align:left"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Hello! <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">I noticed that in some cases clang generates sequence of AND+TST instructions:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">For example:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> AND x3, x2, x1<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> TST x2, x1<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">I think these instructions should be merged to one:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> ANDS x3, x2, x1<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">( because TST <Xn>, <Xm> is alias for ANDS XZR, <Xn>, <Xm> -
<a href="https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf">
https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf</a> )<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Is it missing optimization or there could be some negative effect from such merge?<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Best regards<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Pavel<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">PS: Code sample (though it may be significantly reduced):<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">(clang -target aarch64 sample.c -S -O2 -o sample.S )
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">=========================================================================<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">#define NULL ((void*)0)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">typedef struct {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> unsigned long * res_in;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> unsigned long * proc;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> } fd_set_bits;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">fd_set_bits *gv_fds;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">int g_max_i;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">int LOOP_ITERS_COUNT;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">unsigned DEF_MASK;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">__attribute__((noinline)) int do_test(const int max_iters_count,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> const unsigned long in,
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> const unsigned long out,
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> const unsigned long ex,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> const unsigned long bit_init_val,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> const unsigned long mask) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> int retval = 0;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> for(int k =0 ; k < max_iters_count; k++)
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> fd_set_bits *fds = gv_fds;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> for(int j = 0; j < LOOP_ITERS_COUNT; ++j)
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> if (in) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> retval++;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> fds->proc = NULL;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> if (mask & DEF_MASK) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> fds->proc = NULL;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> return retval;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">}<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">=========================================================================<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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