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Implementing load combine/widening on the IR level sounds like a reasonable enhancement to me. Although, we (Azul) don't have any plans of doing that in the near future.
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<div class="">Artur<br class="">
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<div class="">On 12 Sep 2019, at 00:58, Paweł Bylica <<a href="mailto:chfast@gmail.com" class="">chfast@gmail.com</a>> wrote:</div>
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<div class="">Ok, thanks.</div>
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<div class="">Are there any plans to reintroduce it on the IR level? I'm not confident this is strictly necessary, but in some cases not having load widening ends up really bad.</div>
<div class="">Like in the case where vectorizer tries to do something about it:</div>
<div class=""><a href="https://godbolt.org/z/60RuEw" class="">https://godbolt.org/z/60RuEw</a></div>
<div class=""><a href="https://bugs.llvm.org/show_bug.cgi?id=42708" class="">https://bugs.llvm.org/show_bug.cgi?id=42708</a></div>
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<div class="">At the current state I'm forced to use memset() to express uint64 load from an array of bytes.</div>
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<div class="">// P.<br class="">
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<div dir="ltr" class="gmail_attr">On Thu, Sep 12, 2019 at 4:22 AM Artur Pilipenko <<a href="mailto:apilipenko@azul.com" class="">apilipenko@azul.com</a>> wrote:<br class="">
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<div style="overflow-wrap: break-word;" class="">Hi,
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<div class="">Load widening/combine for the original pattern was implemented in DAG combiner. See:</div>
<div class=""><a href="https://github.com/llvm/llvm-project/blob/23bbeb52f392d88bf0d0527392a7a11561ee09c0/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6872" target="_blank" class="">https://github.com/llvm/llvm-project/blob/23bbeb52f392d88bf0d0527392a7a11561ee09c0/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6872</a></div>
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<div class="">Later a similar transform was introduced fro stores:</div>
<div class=""><a href="https://github.com/llvm/llvm-project/blob/23bbeb52f392d88bf0d0527392a7a11561ee09c0/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6700" target="_blank" class="">https://github.com/llvm/llvm-project/blob/23bbeb52f392d88bf0d0527392a7a11561ee09c0/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6700</a></div>
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<div class="">There is no load widening on the IR level as of now.</div>
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<div class="">Artur<br class="">
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<div class="">On 11 Sep 2019, at 04:47, Paweł Bylica <<a href="mailto:chfast@gmail.com" target="_blank" class="">chfast@gmail.com</a>> wrote:</div>
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<div class="">Hi,</div>
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<div class="">Can I ask what is the status of load widening. It seems there is no load widening on IR at all.</div>
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<div class="">// Paweł<br class="">
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<div dir="ltr" class="gmail_attr">On Wed, Oct 5, 2016 at 1:49 PM Artur Pilipenko via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank" class="">llvm-dev@lists.llvm.org</a>> wrote:<br class="">
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Philip and I talked about this is person. Given the fact that load widening in presence of atomics is irreversible transformation we agreed that we don't want to do this early. For now it can be implemented as a peephole optimization over machine IR. MIR is
preferred here because X86 backend does GEP reassociation at MIR level and it can make information about addresses being adjacent available.<br class="">
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Inline cost of the original pattern is a valid concern and we might want to revisit our decision later. But in order to do widening earlier we need to have a way to undo this transformation.<br class="">
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I’m going to try implementing MIR optimization but not in the immediate future.<br class="">
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Artur<br class="">
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> On 28 Sep 2016, at 19:32, Artur Pilipenko <<a href="mailto:apilipenko@azulsystems.com" target="_blank" class="">apilipenko@azulsystems.com</a>> wrote:<br class="">
> <br class="">
> One of the arguments for doing this earlier is inline cost perception of the original pattern. Reading i32/i64 by bytes look much more expensive than it is and can prevent inlining of interesting function.<br class="">
> <br class="">
> Inhibiting other optimizations concern can be addressed by careful selection of the pattern we’d like to match. I limit the transformation to the case when all the individual have no uses other than forming a wider load. In this case it’s less likely to loose
information during this transformation.<br class="">
> <br class="">
> I didn’t think of atomicity aspect though.<br class="">
> <br class="">
> Artur<br class="">
> <br class="">
>> On 28 Sep 2016, at 18:50, Philip Reames <<a href="mailto:listmail@philipreames.com" target="_blank" class="">listmail@philipreames.com</a>> wrote:<br class="">
>> <br class="">
>> There's a bit of additional context worth adding here...<br class="">
>> <br class="">
>> Up until very recently, we had a form of widening implemented in GVN. We decided to remove this in
<a href="https://reviews.llvm.org/D24096" rel="noreferrer" target="_blank" class="">
https://reviews.llvm.org/D24096</a> precisely because its placement in the pass pipeline was inhibiting other optimizations. There's also a major problem with doing widening at the IR level which is that widening a pair of atomic loads into a single wider atomic
load can not be undone. This creates a major pass ordering problem of its own.<br class="">
>> <br class="">
>> At this point, my general view is that widening transformations of any kind should be done very late. Ideally, this is something the backend would do, but doing it as a CGP like fixup pass over the IR is also reasonable.<br class="">
>> <br class="">
>> With that in mind, I feel both the current placement of LoadCombine (within the inliner iteration) and the proposed InstCombine rule are undesirable.<br class="">
>> <br class="">
>> Philip<br class="">
>> <br class="">
>> <br class="">
>> On 09/28/2016 08:22 AM, Artur Pilipenko wrote:<br class="">
>>> Hi,<br class="">
>>> <br class="">
>>> I'm trying to optimize a pattern like this into a single i16 load:<br class="">
>>> %1 = bitcast i16* %pData to i8*<br class="">
>>> %2 = load i8, i8* %1, align 1<br class="">
>>> %3 = zext i8 %2 to i16<br class="">
>>> %4 = shl nuw i16 %3, 8<br class="">
>>> %5 = getelementptr inbounds i8, i8* %1, i16 1<br class="">
>>> %6 = load i8, i8* %5, align 1<br class="">
>>> %7 = zext i8 %6 to i16<br class="">
>>> %8 = shl nuw nsw i16 %7, 0<br class="">
>>> %9 = or i16 %8, %4<br class="">
>>> <br class="">
>>> I came across load combine pass which is motivated by virtualliy the same pattern. Load combine optimizes the pattern by combining adjacent loads into one load and lets the rest of the optimizer cleanup the rest. From what I see on the initial review for
load combine (<a href="https://reviews.llvm.org/D3580" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/D3580</a>) it was not enabled by default because it caused some performance regressions. It's not very surprising, I see how this type
of widening can obscure some facts for the rest of the optimizer.<br class="">
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>>> I can't find any backstory for this pass, why was it chosen to optimize the pattern in question in this way? What is the current status of this pass?<br class="">
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>>> I have an alternative implementation for it locally. I implemented an instcombine rule similar to recognise bswap/bitreverse idiom. It relies on collectBitParts (Local.cpp) to determine the origin of the bits in a given or value. If all the bits are happen
to be loaded from adjacent locations it replaces the or with a single load or a load plus bswap.<br class="">
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>>> If the alternative approach sounds reasonable I'll post my patches for review.<br class="">
>>> <br class="">
>>> Artur<br class="">
>> <br class="">
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