<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">This is fantastic progress Alex, congratulations. Judging by the official criteria, I think you’re covered if there is a buildbot:<div class=""><a href="http://llvm.org/docs/DeveloperPolicy.html#new-targets" class="">http://llvm.org/docs/DeveloperPolicy.html#new-targets</a></div><div class=""><br class=""></div><div class="">I am also very +1 on including this as an official target assuming that is taken care of, thank you!</div><div class=""><br class=""></div><div class="">-Chris</div><div class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Jul 8, 2019, at 3:19 PM, Alex Bradbury via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">The 9.0 release is currently scheduled to branch in 10 days time, on<br class="">the 18th of July, with a final release expected on 28th August. I<br class="">would like to propose promoting the RISC-V backend from its current<br class="">"experimental" status to "official" prior to this branch. This means<br class="">that the RISC-V backend will be built by default and support included<br class="">in standard binary distributions of LLVM/Clang.<br class=""><br class=""># Status<br class=""><br class="">RISC-V is a modular ISA with 32- and 64-bit variants, as well as a range of<br class="">options specified in "ISA naming strings". The RISC-V backend supports<br class="">both variants and all standard extensions. RV32IMAFDC, RV64IMAFDC, and<br class="">the ilp32, ilp32f, ilp32d, lp64, lp64f, lp64d ABIs (the clang<br class="">hard-float ABI patch will land imminently<br class=""><<a href="https://reviews.llvm.org/D60456" class="">https://reviews.llvm.org/D60456</a>>).<br class=""><br class="">We have a fairly comprehensive out set of in-tree unit tests, multiple<br class="">groups have indicated they are using Clang/LLVM for their RISC-V<br class="">embedded firmware builds and more recently we have been pushing<br class="">forwards on issues related to building Linux/FreeBSD applications. The<br class="">GCC torture suite has a 100% pass rate, we're seeing a 98% pass rate<br class="">on the LLVM test-suite (failures are almost all related to C++<br class="">exception handling, which we hope to resolve soon), and we've been<br class="">able to get over 90% of buildroot's over 20000 packages to build for<br class="">RISC-V using clang, where most failures are due to build system issues<br class="">or GCCisms. We can compile and run meaningful programs (e.g. build a<br class="">rootfs with nginx, serve HTTP requests).<br class=""><br class="">Additionally, I understand that LLD support is now roughly feature-complete<br class="">with the exception of support for linker relaxation. Fangrui Song has been<br class="">most active on RISC-V LLD recently.<br class=""><br class="">There is initial Rust support for bare metal rv32 and rv64, with support for<br class="">hard float Linux targets due to start soon.<br class=""><br class="">I believe that we are ready to flip the switch towards an 'official' target.<br class="">At lowRISC, we're ready to address any issues that arise, and as noted below<br class="">we're delighted that there's a growing community of contributors around this<br class="">backend who are equally invested in its success.<br class=""><br class="">## Thanks<br class=""><br class="">I started work on the RISC-V LLVM backend around the end of 2016<br class="">through lowRISC, a not-for-profit open source hardware/software<br class="">engineering company I co-founded. I'd like to thank everyone who gave<br class="">encouragement, helped with funding in order to support this work, or<br class="">submitted reviews or patches. As well as growing the toolchain team at<br class="">lowRISC (Luís Marques, Sam Elliott, and myself), we've been able to<br class="">help grow a community of contributors around this work. There are far<br class="">too many names to mention, but engineers from organisations such as<br class="">Qualcomm, AndesTech, Embecosm, Google, and the University of Cambridge<br class="">have all made notable contributions.<br class=""><br class="">## End<br class=""><br class="">Although becoming an official backend would be a huge milestone, of course it's<br class="">far from the end of the road. We'll be continuing to work on code size and<br class="">generated code performance improvements, better testing, working with language<br class="">communities like Rust/Swift/Julia/..., support for additional LLVM features<br class="">and RISC-V instruction set extensions, etc.<br class=""><br class="">Any questions / concerns / feedback?<br class=""><br class="">--<br class="">Alex Bradbury,<br class="">CTO and Co-Founder, lowRISC CIC<br class="">_______________________________________________<br class="">LLVM Developers mailing list<br class=""><a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a><br class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev<br class=""></div></div></blockquote></div><br class=""></div></body></html>