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<p class="MsoNormal">Thanks Eli!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I will report the bug.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Eli Friedman <efriedma@quicinc.com> <br>
<b>Sent:</b> Tuesday, June 25, 2019 2:06 PM<br>
<b>To:</b> Chawla, Pankaj <pankaj.chawla@intel.com>; llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Cc:</b> Bakhvalov, Denis <denis.bakhvalov@intel.com><br>
<b>Subject:</b> RE: [llvm-dev] SCEVExpander bug?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Real bug; the shift shouldn’t be marked nsw. (See also <a href="https://github.com/llvm/llvm-project/blob/5e13cd2e61cb187f28d743c15141333530cc1adf/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L177">
https://github.com/llvm/llvm-project/blob/5e13cd2e61cb187f28d743c15141333530cc1adf/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L177</a> .)<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">-Eli<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> llvm-dev <<a href="mailto:llvm-dev-bounces@lists.llvm.org">llvm-dev-bounces@lists.llvm.org</a>>
<b>On Behalf Of </b>Chawla, Pankaj via llvm-dev<br>
<b>Sent:</b> Tuesday, June 25, 2019 1:39 PM<br>
<b>To:</b> <a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a><br>
<b>Cc:</b> Bakhvalov, Denis <<a href="mailto:denis.bakhvalov@intel.com">denis.bakhvalov@intel.com</a>><br>
<b>Subject:</b> [EXT] [llvm-dev] SCEVExpander bug?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">We have recently encountered incorrect code generation issues and I think it is a SCEVExpander bug exposed by a recent patch to add nuw/nsw flags when generating code for SCEVMulExpr.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The test case IR looks like this-<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">%1 = load i16, i16* %arrayidx<o:p></o:p></p>
<p class="MsoNormal">%2 = and i16 %1, -32768<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The SCEV form of %2 is this-<o:p></o:p></p>
<p class="MsoNormal">(-32768 * (%1 /u -32768))<nuw><nsw><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">It has both nsw/nuw flags. The signed range of the second operand of SCEVMulExpr (%1 /u -32768) is [0, 2). So it can be either 0 or 1.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">But SCEVExpander uses shl to generate the multiply. The generated IR looks something like this-<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">%7 = lshr i16 %gepload, 15<o:p></o:p></p>
<p class="MsoNormal">%8 = shl nuw nsw i16 %7, 15<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The issue is that %8 is later simplified to zero because according to langref it produces poison otherwise -<o:p></o:p></p>
<p class="MsoNormal"><i>If the nuw keyword is present, then the shift produces a poison value if it shifts out any non-zero bits. If the nsw keyword is present, then the shift produces a poison value if it shifts out any bits that disagree with the resultant
sign bit.<o:p></o:p></i></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Is this a real bug or am I missing something?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal">Pankaj<o:p></o:p></p>
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