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<span style="color: rgb(51, 51, 51); font-family: Cambria, serif; font-size: 12pt;">Hi all LLVM expert,</span><br>
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<span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)"> </span></p>
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<span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)">I¡¯m trying to ask how to bind hidden micro-architecture specific resource index to architecture resource index in tablegen</span></p>
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<span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)">There may be instruction uses 1 sr and 1 vr as source operand (using index sr_src_idx, vr_src_idx), then uses 1 sr and 1 vr as destination
(using index sr_dst_idx, vr_dst_idx). Additionally, this instruction trigger a write to a hidden resource whose index is same as the vr destination index (vr_dst_idx). The instruction's write to SR/VR/HR are with different latency, say 1/3/6. Example code
are as below</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)"></span></p>
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<span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)">Is there a way to describe this in tablegen? How to bind the index between hr and vr?</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)"></span></p>
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<span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(51, 51, 51)"><br>
</span><span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)">Scalar_Register sr[32]; //architecture visible resource</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)"></span></p>
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<span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)">Vector_Register vr[32]; //architecture visible resource</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)"></span></p>
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<span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)">Hidden_Resource hr[32]; //target specific micro-architecture resource, hidden from architecture but impact performance</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)"></span></p>
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<span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)">//instruction info defined in ISA</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)"></span></p>
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<span style="margin: 0px"><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)">(VR vr_dst_idx, SR sr_dst_idx) = instruciton_1 (VR vr_src_idx, SR sr_src_idx) ;</span></span><span style="margin: 0px; font-size: 12pt; font-family: Cambria, serif; color: rgb(0, 112, 192)"></span></p>
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<span style="margin: 0px; font-family: Cambria, serif">Chuang Feng</span></p>
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