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<p class="MsoNormal">The ARM backend does something similar to what you’re describing for Thumb code; see ARMMCCodeEmitter::encodeInstruction.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">-Eli<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> llvm-dev <llvm-dev-bounces@lists.llvm.org> <b>On Behalf Of
</b>Josh Sharp via llvm-dev<br>
<b>Sent:</b> Monday, June 3, 2019 3:57 PM<br>
<b>To:</b> via llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> [EXT] [llvm-dev] Byte ordering during machine code generation<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Hi,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Is there a way to specify the byte ordering in a way that's neither big nor little endian during machine code generation?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">For example, if B3B2B1B0 is a 32-bit instruction with B3 the most significant byte, is there a way to write it as B1 B0 B3 B2 ?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Thanks. <o:p></o:p></span></p>
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