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<span>Hi all,<br>
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<span><br>
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<span>I'm facing a crash in TableGen (as of 7.0) when generating register info for our out-of-tree target.</span></div>
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<span><br>
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<span>llvm-tblgen: llvm/utils/TableGen/CodeGenRegisters.cpp:128: void llvm::CodeGenSubRegIndex::setConcatenationOf(llvm::ArrayRef<llvm::CodeGenSubRegIndex*>): Assertion `std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin()) && "parts consistent"'
failed.<br>
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<span><br>
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<span>It should reproduce, even on tip, with the example RegisterInfo file I've pasted below. Run with: llvm-tblgen -gen-register-info -I /path/to/llvm/include TestRegInfo.td<br>
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<span><span>It's something to do with SUPER1 and SUPER2</span> using the same index (SubRegLo32) to index subregisters which themselves contain differently-composed subregisters from one another: SuperQ has four quarters but I1 has two halves.</span></div>
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<span>My question is: is this a documented restriction in TableGen or a bug? If it's a design choice, should it emit a more appropriate error rather than asserting?<br>
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<span><br>
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<span>Thanks,</span></div>
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<span>Fraser<br>
</span></div>
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<span><br>
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<span>----------------------------------------------------------</span></div>
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<span>include "llvm/Target/Target.td"<br>
</span>
<div><br>
</div>
<div>class MyReg<string name, list<Register> subregs = []><br>
</div>
<div> : RegisterWithSubRegs<name, subregs> {<br>
</div>
<div> let Namespace = "TST";<br>
</div>
<div>}<br>
</div>
<div><br>
</div>
<div>// Quarter Registers<br>
</div>
<div><br>
</div>
<div>def Q0 : MyReg<"Q0">;<br>
</div>
<div>def Q1 : MyReg<"Q1">;<br>
</div>
<div>def Q2 : MyReg<"Q1">;<br>
</div>
<div>def Q3 : MyReg<"Q1">;<br>
</div>
<div><br>
</div>
<div>def SubRegQ0 : SubRegIndex<8, 0>;<br>
</div>
<div>def SubRegQ1 : SubRegIndex<8, 8>;<br>
</div>
<div>def SubRegQ2 : SubRegIndex<8, 16>;<br>
</div>
<div>def SubRegQ3 : SubRegIndex<8, 24>;<br>
</div>
<div><br>
</div>
<div>let SubRegIndices = [SubRegQ0, SubRegQ1,<br>
</div>
<div> SubRegQ2, SubRegQ3],<br>
</div>
<div> CoveredBySubRegs = 1 in {<br>
</div>
<div> def SuperQ : MyReg<"SuperQ ", [Q0, Q1, Q2, Q3]>;<br>
</div>
<div>}<br>
</div>
<div><br>
</div>
<div>// Half Registers<br>
</div>
<div><br>
</div>
<div>foreach i = 0-5 in {<br>
</div>
<div> def H#i : MyReg<"H"#i>;<br>
</div>
<div>}<br>
</div>
<div><br>
</div>
<div>def SubRegLo16 : SubRegIndex<16, 0>;<br>
</div>
<div>def SubRegHi16 : SubRegIndex<16, 16>;<br>
</div>
<div><br>
</div>
<div>// Whole Registers<br>
</div>
<div><br>
</div>
<div>let SubRegIndices = [SubRegLo16, SubRegHi16], CoveredBySubRegs = 1 in {<br>
</div>
<div> def I0 : MyReg<"I0", [H0, H1]>;<br>
</div>
<div> def I1 : MyReg<"I1", [H2, H3]>;<br>
</div>
<div> def I2 : MyReg<"I2", [H4, H5]>;<br>
</div>
<div>}<br>
</div>
<div><br>
</div>
<div>// Super Registers<br>
</div>
<div><br>
</div>
<div>def SubRegLo32 : SubRegIndex<32, 0>;<br>
</div>
<div>def SubRegHi32 : SubRegIndex<32, 32>;<br>
</div>
<div><br>
</div>
<div>let SubRegIndices = [SubRegLo32, SubRegHi32], CoveredBySubRegs = 1 in {<br>
</div>
<div> def SUPER1 : MyReg<"SUPER1", [SuperQ, I0]>;<br>
</div>
<div> def SUPER2 : MyReg<"SUPER2", [I1, I2]>;<br>
</div>
<div>}<br>
</div>
<div><br>
</div>
<div>def TST : Target;<br>
</div>
<div><br>
</div>
<div>class MyClass<int size, list<ValueType> types, dag registers><br>
</div>
<div> : RegisterClass<"Test", types, size, registers> {<br>
</div>
<div> let Size = size;<br>
</div>
<div>}<br>
</div>
<div><br>
</div>
<div>def MyRegs : MyClass<32, [i32], (add I0, I1, I2)>;<br>
</div>
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