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<p class="MsoNormal">You could create a target-specific instruction, or you could pattern-match the copy+sub or copy+sub+copy combination in your Select() implementation in ISelDAGToDAG. Or you could just ignore the potential optimization, like we do on Thumb1;
dynamic stack allocation is generally rare.<o:p></o:p></p>
<p class="MsoNormal"><o:p></o:p></p>
<p class="MsoNormal">-Eli<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Joan Lluch <joan.lluch@icloud.com> <br>
<b>Sent:</b> Tuesday, May 28, 2019 12:36 PM<br>
<b>To:</b> Eli Friedman <efriedma@quicinc.com><br>
<b>Cc:</b> llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> [EXT] Re: [llvm-dev] Instruction is selected, but it shouldn't (?)<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi Eli,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions. The issue appears when trying to use the SP in iSelLowering, in particular,
I attempt to create a LowerDYNAMIC_STACKALLOC function similar to the Thumb1. However, since my SP register is not part of the set of General Purpose registers, and the SP only has special instructions for it, I can NOT use the Thumb1 code implementation below:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif;color:#4F8187">SDValue</span><span style="font-size:8.5pt;font-family:"Monaco",serif"> SP = DAG.<span style="color:#31595D">getCopyFromReg</span>(Chain, DL,
<span style="color:#4F8187">ARM</span>::<span style="color:#31595D">SP</span>, <span style="color:#4F8187">
MVT</span>::<span style="color:#31595D">i32</span>);<o:p></o:p></span></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">Chain = SP.<span style="color:#31595D">getValue</span>(<span style="color:#272AD8">1</span>);<o:p></o:p></span></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">SP = DAG.<span style="color:#31595D">getNode</span>(<span style="color:#4F8187">ISD</span>::<span style="color:#31595D">SUB</span>, DL,
<span style="color:#4F8187">MVT</span>::<span style="color:#31595D">i32</span>, SP, Size);<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I must use this instead:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif;color:#4F8187">SDValue</span><span style="font-size:8.5pt;font-family:"Monaco",serif"> SP = DAG.<span style="color:#31595D">getRegister</span>(<span style="color:#4F8187">CPU74</span>::<span style="color:#31595D">SP</span>,
VT);<o:p></o:p></span></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">SP = DAG.<span style="color:#31595D">getNode</span>(<span style="color:#4F8187">ISD</span>::<span style="color:#31595D">SUB</span>, dl,
<span style="color:#4F8187">MVT</span>::<span style="color:#31595D">i16</span>, SP, Size);<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The ‘getCopyFromReg’ code in the first excerpt produces suboptimal code because LLVM can not figure out a way to place the SP directly in the SUB instruction without using an intermediate register. <o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">However, the code on the second excerpt produces optimal code, except that the wrong instruction is selected…<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">So, what do you suggest for me to do?. Maybe creating a Target Specific ISD instruction for that SUB that gets correctly selected during iSelDagToDag?<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif;color:black">Joan Lluch<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On 28 May 2019, at 20:55, Eli Friedman <<a href="mailto:efriedma@quicinc.com">efriedma@quicinc.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">SelectionDAG isel is only driven by types and operations; it doesn’t care about specific registers. So you have to pick one version of “add” you want isel to use by default (in this case, probably the general-register version), and only
specify a pattern for that one.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">For computing the addresses of stack slots in particular, you might want to look at how the ARM backend generates Thumb1 code. Thumb1 has special instructions for SP-relative accesses (tADDframe, tADDrSP, tADDrSPi, tLDRspi, tSTRspi). Explicit
copies from “sp” don’t really come up during isel, except for call arguments; most of the interesting code is part of frame lowering.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">-Eli<span class="apple-converted-space"> </span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b><span class="apple-converted-space"> </span>llvm-dev <<a href="mailto:llvm-dev-bounces@lists.llvm.org">llvm-dev-bounces@lists.llvm.org</a>><span class="apple-converted-space"> </span><b>On Behalf Of<span class="apple-converted-space"> </span></b>Joan
Lluch via llvm-dev<br>
<b>Sent:</b><span class="apple-converted-space"> </span>Tuesday, May 28, 2019 11:31 AM<br>
<b>To:</b><span class="apple-converted-space"> </span>via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>><br>
<b>Subject:</b><span class="apple-converted-space"> </span>[EXT] [llvm-dev] Instruction is selected, but it shouldn't (?)<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">def GR16 : RegisterClass<<span style="color:#D12F1B">"CPU74"</span>, [i16],<span class="apple-converted-space"> </span><span style="color:#272AD8">16</span>,
(add R0, R1, R2, R3, R4, R5, R6, R7)>;</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">def SSP : RegisterClass<<span style="color:#D12F1B">"CPU74"</span>, [i16],<span class="apple-converted-space"> </span><span style="color:#272AD8">16</span>,
(add SP)>;</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td:<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<<span style="color:#272AD8">4</span>> opcode>: Type5</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> <opcode,</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> (outs GR16:$rd), (ins GR16:$rn, GR16:$rs),</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> AsmStr< opcStr, altOpcStr,<span class="apple-converted-space"> </span><span style="color:#D12F1B">"\t$rn, $rs, $rd"</span>>.n,</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> [(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit SR)]>;</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> </span><o:p></o:p></p>
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<p class="MsoNormal">I also have specific instructions that can only use the SP, so I defined this as well<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif">class T11sr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<<span style="color:#272AD8">3</span>> opcode, bits<<span style="color:#272AD8">2</span>>
mode>: Type11</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> <opcode, mode,</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> (outs GR16:$rd), (ins SSP:$sp, GR16:$rd0),</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> AsmStr< opcStr, altOpcStr,<span class="apple-converted-space"> </span><span style="color:#D12F1B">"\t$sp, $rd0, $rd"</span>>.n,</span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> [(set GR16:$rd, (opNode SSP:$sp, GR16:$rd0)), (implicit SR)]></span><o:p></o:p></p>
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<p class="MsoNormal" style="background:white"><span style="font-size:8.5pt;font-family:"Monaco",serif"> {let Constraints =<span class="apple-converted-space"> </span><span style="color:#D12F1B">"$rd = $rd0"</span>;}</span><o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">According to my understanding, instructions belonging to the T5rr16alu class above, should never be selected with the SP as register. However, instructions of that class get selected anyway with the SP, instead of the class T11sr16alu.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">However, if I place class T11sr16alu, before class T5rr16alu, then the right instruction is selected<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Why is that?. <o:p></o:p></p>
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<p class="MsoNormal">What I am missing?<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif">Joan</span><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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