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<p>Hi Quentin,</p>
<p>MyInst is a custom instruction that has implicit-defs of fixed
registers. The implicit-defs are seen at the end of Instruction
Selection. <br>
I'd like to add a report, but I am working on an out-of-tree
backend based on 7.0. I can try to help reduce the testcase down.<br>
Filed <a class="moz-txt-link-freetext" href="https://bugs.llvm.org/show_bug.cgi?id=41790">https://bugs.llvm.org/show_bug.cgi?id=41790</a><br>
</p>
<p>Regards,<br>
Kevin<br>
</p>
<div class="moz-cite-prefix">On 2019-05-07 3:45 p.m., Quentin
Colombet wrote:<br>
</div>
<blockquote type="cite"
cite="mid:0F7DC12B-58E7-434A-896D-92DF3F72058A@apple.com">
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Hi Kevin,
<div class=""><br class="">
</div>
<div class="">That sounds like a bug :).</div>
<div class=""><br class="">
</div>
<div class="">When is the implicit-def added?</div>
<div class=""><br class="">
</div>
<div class="">What I am thinking is if it gets added after we
computed the live intervals, then we may miss it is there.</div>
<div class=""><br class="">
</div>
<div class="">Could you file a public report?</div>
<div class=""><br class="">
</div>
<div class="">Thanks,</div>
<div class="">-Quentin<br class="">
<div><br class="">
<blockquote type="cite" class="">
<div class="">On May 6, 2019, at 3:13 PM, Kevin Choi via
llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org"
class="" moz-do-not-send="true">llvm-dev@lists.llvm.org</a>>
wrote:</div>
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<p class="">Hi LLVM,</p>
<p class="">I ran into a case where RegAlloc would
insert a spill across instruction that had same
register for output operand and implicit-def. The
effect this had was that spill code would immediately
overwrite the output result. Is this the expected
result of setting up MyInst this way? In other words,
does RegAlloc know to not insert spill in case it sees
that output reg is same as one of implicit-def?</p>
<p class="">If this is intended (always spilling live
regs across implicit-def inst?), I am puzzled on how
to use MyInst that has variable output reg with static
implicit-defs. Any tips would be greatly appreciated.</p>
<p class="">Reduced Example:<br class="">
</p>
<p class=""><u class=""><b class="">Before RegAlloc:</b></u><br
class="">
%1:reg = COPY ...;<br class="">
%2:reg = MyInst %1:reg, ..., implicit-def dead $p1,
...;<br class="">
%3:reg = Use %2:reg</p>
<u class=""><b class="">RegAlloc:</b></u><br class="">
>> %2:reg = MyInst %1:reg, ..., implicit-def dead
$p1, ...;<br class="">
Regs: $p1=%1<br class="">
Killing last use: %1:reg<br class="">
Assigning %2 to $p1<br class="">
Spilling %2 in $p1 to stack slot #2 <-- suspicious
if this is inserting spill, unaware of output reg being
same<br class="">
<< $p1 =MyInst killed $p1, ..., implicit-def dead
$p1, ...;
<p class=""><b class=""><u class="">After RegAlloc:</u></b><br
class="">
$p1 = COPY ...;<br class="">
Store $p1 %stack.2;<br class="">
$p1 =MyInst killed $p1, ..., implicit-def dead $p1,
...;<br class="">
$p1 = Load %stack.2;<br class="">
$p2 = Use $p1, ...;</p>
<p class=""><br class="">
</p>
<p class="">Best Regards,</p>
<p class="">Kevin<br class="">
</p>
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