<div dir="ltr"><div dir="ltr">It's in ARMRegisterInfo.td<div><br></div><div><div>// Thumb registers are R0-R7 normally. Some instructions can still use</div><div>// the general GPR register class above (MOV, e.g.)</div><div>def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {</div><div> let DiagnosticString = "operand must be a register in range [r0, r7]";</div><div>}</div></div><div><br clear="all"><div><div dir="ltr" class="gmail_signature">~Craig</div></div><br></div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sun, Apr 14, 2019 at 12:38 PM Jie Zhou <<a href="mailto:jzhou41@cs.rochester.edu">jzhou41@cs.rochester.edu</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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Hi Craig,
<div><br>
</div>
<div>Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7?</div>
<div>I tried to search in ARMInstrThumb.td but couldn’t find it.</div>
<div><br>
</div>
<div>Thanks,</div>
<div>- Jie<br>
<div><br>
<blockquote type="cite">
<div>On Apr 14, 2019, at 15:28, Craig Topper <<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>> wrote:</div>
<br class="gmail-m_-4165026908401281747Apple-interchange-newline">
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<div dir="ltr">
<div dir="ltr">I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2 instead of t.
<div><br>
</div>
<div>The definition of tADDi8 looks like this. Where tGPR specifically means R0-R7.</div>
<div><br>
</div>
<div>
<div> def tADDi8 : // A8.6.4 T2</div>
<div> T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),</div>
<div> (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,</div>
<div> "add", "\t$Rdn, $imm8",</div>
<div> [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,</div>
<div> Sched<[WriteALU]>;</div>
<div><br clear="all">
<div>
<div dir="ltr" class="gmail-m_-4165026908401281747gmail_signature">~Craig</div>
</div>
<br>
</div>
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</div>
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<br>
<div class="gmail_quote">
<div dir="ltr" class="gmail_attr">On Sun, Apr 14, 2019 at 12:21 PM Jie Zhou <<a href="mailto:jzhou41@cs.rochester.edu" target="_blank">jzhou41@cs.rochester.edu</a>> wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div>Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2.
<div>It has 12 regular registers (R0 - R12), and R8 - R12 are used. </div>
<div>I can generate mov instruction that from/ R8-R12 to/from R0-R6. </div>
<div>From this ARM page <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__infocenter.arm.com_help_index.jsp-3Ftopic-3D_com.arm.doc.dui0068b_ch03s03s01.html&d=DwMFaQ&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=KAtyTEI8n3FritxDpKpR7rv3VjdmUs0luiVKZLb_bNI&m=_fpYL_7E5zOQ4DZeiPmiSOgKp7KxZ5mAZVh9wB6CxUY&s=1r2JmIRDr3fxySkwnQU16zv8ySZfoc3nUtLdCcwb4gw&e=" target="_blank">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html</a></div>
<div>R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot </div>
<div>use them arbitrarily. The fact that we can use it to generate mov instructions but</div>
<div>not add/sub and push/pop confuses me.</div>
<div><br>
</div>
<div>- Jie<br>
<div><br>
<blockquote type="cite">
<div>On Apr 14, 2019, at 14:55, Craig Topper <<a href="mailto:craig.topper@gmail.com" target="_blank">craig.topper@gmail.com</a>> wrote:</div>
<br class="gmail-m_-4165026908401281747gmail-m_4679658289449006096Apple-interchange-newline">
<div>
<div dir="ltr">I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7.
<div><br>
</div>
<div>tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument.<br>
<div><br clear="all">
<div>
<div dir="ltr" class="gmail-m_-4165026908401281747gmail-m_4679658289449006096gmail_signature">~Craig</div>
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<div dir="ltr" class="gmail_attr">On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>> wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
Hi all,<br>
<br>
I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird.<br>
For an add, when I use <br>
<br>
BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm).<br>
<br>
if reg is R0 - R7, everything is fine: I would get something like<br>
<br>
adds r1, 4<br>
<br>
But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get
<br>
<br>
adds r0, 4<br>
<br>
rather than<br>
<br>
adds r8, 4.<br>
<br>
Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0 - R7, but<br>
for registers whose number are greater than R7, the generated asm code doesn’t have it. For example,
<br>
<br>
BuildMI(……, TII->get(ARM::tPUSH), R8)…..<br>
<br>
would give me <br>
<br>
push {}<br>
<br>
Is this a bug in the LLVM ARM code generator? Or is there a reason why we cannot use big-number registers for add/sub and push/pop?
<br>
<br>
Thanks,<br>
- Jie<br>
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