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<p class="MsoNormal"><a href="https://github.com/llvm/llvm-project/blob/7a8e505/llvm/lib/Target/ARM/ARMISelLowering.cpp#L8481">https://github.com/llvm/llvm-project/blob/7a8e505/llvm/lib/Target/ARM/ARMISelLowering.cpp#L8481</a> has the correct invocation. You
should have been able to find this using “grep”. More generally, if you’re curious how an instruction is represented, you can instruct the compiler to print the IR/MIR for a file at various stages using “-print-after-all” (“-mllvm -print-after-all” from clang).<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">ARM supports conditional execution; the predicate operands are used to represent that. This is represented with two operands; the predicate code (“al”, “eq”, “ne”, etc.), and the register that controls predication (%noreg if it’s not predicated,
$cpsr if it is).<o:p></o:p></p>
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<p class="MsoNormal">-Eli <o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> llvm-dev <llvm-dev-bounces@lists.llvm.org> <b>On Behalf Of
</b>Jie Zhou via llvm-dev<br>
<b>Sent:</b> Wednesday, March 20, 2019 5:53 PM<br>
<b>To:</b> via llvm-dev <llvm-dev@lists.llvm.org><br>
<b>Subject:</b> [EXT] [llvm-dev] How to build an ARM Thumb2 ADD with shift immediate Machine Instruction<o:p></o:p></p>
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<p class="MsoNormal">Hello,<o:p></o:p></p>
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<p class="MsoNormal">I’m trying to build an "ADD with shift immediate" machine instruction (ADD(register) Encoding T3; item A7.7.4 of the ARMv7-M manual) in an ARM machine function pass. Here is my code<o:p></o:p></p>
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<p class="MsoNormal"> BuildMI(...., TII->get(ARM::t2ADDrs), r1).addReg(r1).addReg(r1).addReg(r2).addImm(imm);<o:p></o:p></p>
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<p class="MsoNormal">This code can compile, but I got a failed assertion <o:p></o:p></p>
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<p class="MsoNormal"> Assertion `idx < size()' failed. <o:p></o:p></p>
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<p class="MsoNormal">thrown by llvm/include/llvm/ADT/SmallVector.h. when I compile test program with the pass.<o:p></o:p></p>
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<p class="MsoNormal">I tried to tweak the registers and immediates added to the BuildMI() but haven't succeeded.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Can anyone give me some direction on how to tackle this problem?<o:p></o:p></p>
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<p class="MsoNormal">Also, can anyone explain to me what <o:p></o:p></p>
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<p class="MsoNormal"> pred:14<o:p></o:p></p>
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<p class="MsoNormal">and <o:p></o:p></p>
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<p class="MsoNormal"> pred:%noreg<o:p></o:p></p>
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<p class="MsoNormal">mean in ARM machine instructions? I see them everywhere.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal">-Jie<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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