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Hello Anmol,<br>
<br>
Thank you for your support. I think that community help could
accelerate integration of backend, so I will keep in mind your
suggestions. By the way it will useful to know what kind of task do
you solve with Xtensa processors and also which Xtensa
configuration do you use(of cause if it is not confidential
information). Such information could help to tune some aspects of
the Xtensa backend.<br>
<br>
Best regards,<br>
Andrei Safronov
<div class="moz-cite-prefix">09.03.2019 1:44, Anmol Paralkar
(anmparal) пишет:<br>
</div>
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<p class="MsoNormal"><span style="color:black">Hello </span><span
style="font-size:10.5pt">Andrei,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:black"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:black">Thank you for the
LLVM Xtensa work and the post. Cisco Systems would be glad
to support any upstreaming effort for this work in terms of
reviews, tests, object file generation, further development,
etc.</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Best Regards,<o:p></o:p></p>
<p class="MsoNormal">Anmol P. Paralkar<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b><span
style="font-size:12.0pt;color:black">From: </span></b><span
style="font-size:12.0pt;color:black">llvm-dev
<a class="moz-txt-link-rfc2396E" href="mailto:llvm-dev-bounces@lists.llvm.org"><llvm-dev-bounces@lists.llvm.org></a> on behalf of
Andrei Safronov via llvm-dev
<a class="moz-txt-link-rfc2396E" href="mailto:llvm-dev@lists.llvm.org"><llvm-dev@lists.llvm.org></a><br>
<b>Reply-To: </b>Andrei Safronov
<a class="moz-txt-link-rfc2396E" href="mailto:safronov@espressif.com"><safronov@espressif.com></a><br>
<b>Date: </b>Wednesday, March 6, 2019 at 5:30 AM<br>
<b>To: </b><a class="moz-txt-link-rfc2396E" href="mailto:llvm-dev@lists.llvm.org">"llvm-dev@lists.llvm.org"</a>
<a class="moz-txt-link-rfc2396E" href="mailto:llvm-dev@lists.llvm.org"><llvm-dev@lists.llvm.org></a><br>
<b>Subject: </b>[llvm-dev] [RFC] Tensilica Xtensa (ESP32)
backend<o:p></o:p></span></p>
</div>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span
style="font-size:10.5pt;font-family:"-moz-fixed",serif">Hello,
<br>
<br>
I'm from Espressif Systems company, software department.
Our company develops processors based on Xtensa
architecture like ESP32 and ESP8266. We propose the
integration of a backend targeting Xtensa architecture.
<br>
<br>
We started to develop LLVM Xtensa backend almost a year
ago. The reason was that we saw a demand from our large
developers community. Currently only GNU compiler supports
Xtensa architecture. The company has approved me to
develop and maintain Xtensa backend.
<br>
<br>
We already have the initial version of the Xtensa backend,
based on LLVM Compiler Infrastructure, release 6.0.0. It
was successfully tested using GCC torture testsuite and
multiple applications.
<br>
<br>
These are the links to LLVM and Clang repositories. <br>
<br>
<a href="https://github.com/espressif/llvm-xtensa"
moz-do-not-send="true">https://github.com/espressif/llvm-xtensa</a>
<br>
<a href="https://github.com/espressif/clang-xtensa"
moz-do-not-send="true">https://github.com/espressif/clang-xtensa</a>
<br>
<br>
Current version can generate Xtensa assembly code as
output, not object files yet, and has to be used together
with GNU Binutils and GCC-built libraries to create object
and binary files.
<br>
<br>
Xtensa backend features implemented: <br>
<br>
- Xtensa target description(Xtnesa.td,
XtensaTargetMachine.cpp, XtensaSubTarget.cpp)
<br>
- ISA desciption (XtensaInstrInfo.td,
XtensaInstrFormats.td, XtensaREgisterInfo.td)
<br>
- Xtensa Call ABI (XtensaCallingConv.td,
XtensaFrameLowering.cpp) <br>
- ASM printer/parser(XtesaAsmPrinter.cpp,
XtensaInstrPrinter.cpp, XtensaAsmParser.cpp)
<br>
<br>
Xtensa architecture features implemented in compiler: <br>
<br>
- Xtensa Core Architecture instructions <br>
- Code Density option <br>
- Windowed Register option <br>
- Floating-Point Coprocessor option <br>
- Boolean option (only a subset of instructions) <br>
- Thread Pointer option <br>
- atomic operations <br>
<br>
Current Xtensa target list: <br>
<br>
- support Xtensa LX6 target (ESP32) by default <br>
<br>
Compiler optimization levels include O0/O1/O2/O3/Os
options. <br>
<br>
With LLVM community approval, my next plans will be <br>
<br>
- rebasing on the upstream version of LLVM. <br>
- object code generation (XtensaMC package) <br>
- implement test cases <br>
- support for LX106 target (ESP8266) <br>
- improvements of generated code performance <br>
- support for zero-overhead loop option <br>
- MAC16 option <br>
<br>
There were some discussions about implementation of the
Xtensa backend and attempt to implement it:
<br>
<a
href="http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html"
moz-do-not-send="true">http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html</a>
<br>
<a
href="http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html"
moz-do-not-send="true">http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html</a>
<br>
<br>
Also there were attempts to implement a LLVM Xtensa
backend, but recently I found only one actual link:
<br>
<a href="https://github.com/jdiez17/llvm-xtensa"
moz-do-not-send="true">https://github.com/jdiez17/llvm-xtensa</a>
<br>
<br>
All comments and suggesions are welcome! <br>
<br>
Andrei Safronov <o:p></o:p></span></p>
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