<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Mar 7, 2019 at 12:47 PM Andrei Safronov <<a href="mailto:safronov@espressif.com" target="_blank">safronov@espressif.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<p>Hello, James,<br>
<br>
Thank you very much for your advices! The next step in compiler
development on Espressif is object file generation. There are no
essential problems with this step, it will be implemented in
nearest future. Currently Xtensa backend is able to print and
parse assembly, I used about 1300 tests from gcc torture testsuite
and GNU binutils to debug assembly output and now all tests could
be compiled and executed successfully. So, with object file
generation Xtensa backend will be significally closer to be used
in real projects, but I'm agree that it is not ready yet for
upstreaming. There is no llvm tests and also it is hard to review
such big amount of code. So I need to do something with these
issues.<br>
<br>
I reviewed integration process of the RISC-V backend, which you
mentioned. Did I understand correctly that you suggest to split
the proposed Xtensa backend into ordered patches, each of which
defines some backend functionality (starting from Asm/MC
layer)that is easy to review? And also include in each patch some
set of tests to verify such functionality?</p>
<p></p></div></blockquote><div>Yes, exactly.</div><div><br></div><div>It's not important to follow exactly the same breakup as the RISCV target, but it makes sense to follow roughly the same order of work.</div><div><div><br></div><div>That is, the overall stages you'll want to tackle are going to be something like:</div><div>1. Initial addition of the target, triple parsing, etc. (riscv patches #2 through #4)<br></div><div>2. Working MC for the baseline ISA, (#5 through #11).</div><div>3. Codegen for the baseline ISA (#12-#32)</div><div>4. MC layer for ISA extensions (#33-#41)</div><div>5. Codegen for ISA extensions, and further fixes throughout (#42-...)</div><div><br></div></div><div>Having patches that are small enough to be usefully-reviewable is very helpful, and each patch should have a full set of test-cases included testing its functionality (as much as is feasible).</div><div><br></div><div>But it's also important to be able to see enough of the implementation to have the necessary context to sanely review. So, that's why I suggest that your initial goal should be to create a set of patches fully-implementing just the first two items on that list, and post them for review at the same time. After that's committed, move on to extracting patches for further functionality, adding tests, and posting for review as you go.</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div bgcolor="#FFFFFF"><p>Best regards, <br>
Andrei Safronov<br>
</p>
<div class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673moz-cite-prefix">07.03.2019 1:31, James Y Knight пишет:<br>
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<div dir="ltr">Sounds like a good idea to me! It seems there's
plenty of interest in this architecture.
<div><br>
</div>
<div>From a quick glance at your existing code, it looks
like you haven't added any llvm tests -- that'll certainly
be a requirement. But barring some particular reason why
it's not feasible, I think that having object-file
generation working is basically considered a requirement
for new architectures. (It's also not clear to me why you
cannot with your current code, it looks like instruction
definitions already have their encodings specified and
such).</div>
<div><br>
</div>
<div>If you haven't yet, you ought to check out at the great
patch series that Alex Bradbury created to demonstrate the
addition of RISCV support to LLVM, as a guide to what
order it probably makes sense to make the changes, and how
to split the changes into reviewable pieces for
upstreaming: <a href="https://github.com/lowRISC/riscv-llvm" target="_blank">https://github.com/lowRISC/riscv-llvm</a></div>
<div><br>
</div>
<div>
<div>I'd suggest as your first step, you should work on
getting just the Asm/MC layer rebased onto trunk and
working for the core ISA for your target -- able to
parse and print assembly, both textual and object files
-- with a full suite of test-cases at each step. Just
like the first ~10 patches in the above patchset.</div>
<br class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-Apple-interchange-newline">
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<div dir="ltr" class="gmail_attr">On Wed, Mar 6, 2019 at 6:29 AM
Andrei Safronov via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>>
wrote:<br>
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<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<p> </p>
<div class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-m_-3906164681750564834gmail-m_715095656130124833moz-text-flowed" style="font-family:-moz-fixed;font-size:14px" lang="x-unicode">Hello, <br>
<br>
I'm from Espressif Systems company, software department.
Our company develops processors based on Xtensa
architecture like ESP32 and ESP8266. We propose the
integration of a backend targeting Xtensa architecture. <br>
<br>
We started to develop LLVM Xtensa backend almost a year
ago. The reason was that we saw a demand from our large
developers community. Currently only GNU compiler supports
Xtensa architecture. The company has approved me to
develop and maintain Xtensa backend. <br>
<br>
We already have the initial version of the Xtensa backend,
based on LLVM Compiler Infrastructure, release 6.0.0. It
was successfully tested using GCC torture testsuite and
multiple applications. <br>
<br>
These are the links to LLVM and Clang repositories. <br>
<br>
<a class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="https://github.com/espressif/llvm-xtensa" target="_blank">https://github.com/espressif/llvm-xtensa</a>
<br>
<a class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="https://github.com/espressif/clang-xtensa" target="_blank">https://github.com/espressif/clang-xtensa</a>
<br>
<br>
Current version can generate Xtensa assembly code as
output, not object files yet, and has to be used together
with GNU Binutils and GCC-built libraries to create object
and binary files. <br>
<br>
Xtensa backend features implemented: <br>
<br>
- Xtensa target description(Xtnesa.td,
XtensaTargetMachine.cpp, XtensaSubTarget.cpp) <br>
- ISA desciption (XtensaInstrInfo.td,
XtensaInstrFormats.td, XtensaREgisterInfo.td) <br>
- Xtensa Call ABI (XtensaCallingConv.td,
XtensaFrameLowering.cpp) <br>
- ASM printer/parser(XtesaAsmPrinter.cpp,
XtensaInstrPrinter.cpp, XtensaAsmParser.cpp) <br>
<br>
Xtensa architecture features implemented in compiler: <br>
<br>
- Xtensa Core Architecture instructions <br>
- Code Density option <br>
- Windowed Register option <br>
- Floating-Point Coprocessor option <br>
- Boolean option (only a subset of instructions) <br>
- Thread Pointer option <br>
- atomic operations <br>
<br>
Current Xtensa target list: <br>
<br>
- support Xtensa LX6 target (ESP32) by default <br>
<br>
Compiler optimization levels include O0/O1/O2/O3/Os
options. <br>
<br>
With LLVM community approval, my next plans will be <br>
<br>
- rebasing on the upstream version of LLVM. <br>
- object code generation (XtensaMC package) <br>
- implement test cases <br>
- support for LX106 target (ESP8266) <br>
- improvements of generated code performance <br>
- support for zero-overhead loop option <br>
- MAC16 option <br>
<br>
There were some discussions about implementation of the
Xtensa backend and attempt to implement it: <br>
<a class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html" target="_blank">http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html</a>
<br>
<a class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html" target="_blank">http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html</a>
<br>
<br>
Also there were attempts to implement a LLVM Xtensa
backend, but recently I found only one actual link: <br>
<a class="m_4822972788407137445m_5806498832629024187m_3270012159044945374gmail-m_822862610560206673gmail-m_-3906164681750564834gmail-m_715095656130124833moz-txt-link-freetext" href="https://github.com/jdiez17/llvm-xtensa" target="_blank">https://github.com/jdiez17/llvm-xtensa</a>
<br>
<br>
All comments and suggesions are welcome! <br>
<br>
Andrei Safronov <br>
<br>
</div>
</div>
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