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<div style="font-family:Calibri,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)">
Tim,</div>
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<br>
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I was able to fold the <font size="2"><span style="font-size:11pt">stack address calculation into the load operation as you said. Is the approach the same if I want to fold any target instruction into any another target instruction? Specifically, I'm trying
to get from this</span></font></div>
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<font size="2"><span style="font-size:11pt"><br>
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<span>t0: ch = EntryToken<br>
</span>
<div> t8: i32 = MOVRI TargetConstant:i32<0><br>
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<div> t1: i32,i1,i1,i1,i1 = ADDR TargetFrameIndex:i32<0>, t8<br>
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<div> t3: ch,glue = CopyToReg t0, Register:i32 $r4, t1<br>
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<div> t4: ch = JLR Register:i32 $r4, t3, t3:1<br>
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<br>
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to this<br>
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<br>
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<span>t0: ch = EntryToken<br>
</span>
<div> t1: i32,i1,i1,i1,i1 = ADDR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1<br>
</div>
<div> t3: ch,glue = CopyToReg t0, Register:i32 $r4, t1<br>
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<div> t4: ch = JLR Register:i32 $r4, t3, t3:1</div>
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<font size="2"><span style="font-size:11pt">Thanks.<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Tim Northover <t.p.northover@gmail.com><br>
<b>Sent:</b> Saturday, January 26, 2019 12:15 AM<br>
<b>To:</b> Josh Sharp<br>
<b>Cc:</b> via llvm-dev<br>
<b>Subject:</b> Re: [llvm-dev] Different SelectionDAGs for same CPU</font>
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<div class="PlainText">On Sat, 26 Jan 2019 at 00:15, Josh Sharp <mm92126@hotmail.com> wrote:<br>
> >That C++ function is probably what looks for an FrameIndex node and<br>
> >has been taught that it can be folded into the load.<br>
><br>
> How do you teach a function that a node can be folded into an instruction?<br>
<br>
Well, if you look at the SelectAddrModeIndexed function in<br>
AArch64ISelDAGToDAG.cpp for example, at the top it checks whether the<br>
address we're selecting is an ISD::FrameIndex; if so, it converts it<br>
into an equivalent TargetFrameIndex (so that LLVM knows it's already<br>
been selected) and makes that the base of the address operand, and<br>
adds a dummy TargetConstant 0 as the offset operand; then it returns<br>
true to indicate it was able to match part of the DAG for that<br>
instruction.<br>
<br>
Other key things to look at in that particular example is the<br>
am_indexed8 definition, which is where TableGen is taught about that<br>
C++ function (well, actually SelectAddrMode8, but that just<br>
immediately calls SelectAddrMode with an extra "8" argument), and the<br>
definition of LDRB which uses that am_indexed8 in a pattern.<br>
<br>
The definitions are quite a maze of multiclass expansions, so I<br>
sometimes find it easier to run llvm-tblgen without a backend (from my<br>
build directory "bin/llvm-tblgen ../llvm/lib/Target/AArch64/AArch64.td<br>
-I ../llvm/include -I ../llvm/lib/Target/AArch64"). That expands<br>
everything so that you can (say) look at all the parts that make up<br>
LDRBui (the key instruction) in one place -- all of its operands and<br>
patterns and bits etc.<br>
<br>
Cheers.<br>
<br>
Tim.<br>
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