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<p>Hi,<br>
</p>
<div class="moz-cite-prefix">On 1/31/19 11:20 PM, Jacob Lifshay
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:CAC2bXD7WZcoHbr_HTnJjbkt=WXKONArKNhCHiO9YuXaeFePhZA@mail.gmail.com">
<meta http-equiv="content-type" content="text/html; charset=UTF-8">
<div dir="auto">We're in-progress designing a RISC-V extension (<a
href="http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html"
moz-do-not-send="true">http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html</a>)
that would have variable-length vectors of short vectors (1 to
4):
<div dir="auto"><VL x <4 x float>></div>
<div dir="auto">where each predicate bit masks out a whole short
vector. We're using this extension to vectorize graphics code
where where variables in the pre-vectorization code are short
vectors.</div>
<div dir="auto">So, vectorizing code like:<br>
</div>
<div dir="auto">for(int i = 0; i < 1000; i++)</div>
<div dir="auto">{</div>
<div dir="auto"> vec4 color = colors[i];</div>
<div dir="auto"> vec3 normal = normals[i];</div>
<div dir="auto"> color.rgb *= fmax(0.0, dot(normal,
light_dir));</div>
<div dir="auto"> colors[i] = color;</div>
<div dir="auto">}</div>
<div dir="auto"><br>
</div>
<div dir="auto">
<div dir="auto" style="font-family:sans-serif">I'm planning on
passing already vectorized code into LLVM and using LLVM as
a backend for optimization and JIT code generation.</div>
</div>
<div dir="auto"><br>
</div>
<div dir="auto">Do you think the EVL proposal would support an
ISA like this as it's currently written (by pattern matching
on predicate expansion and vector-length multiplication)?</div>
<div dir="auto">Or, do you think the EVL proposal would need
modification to effectively support this (by adding a element
group size argument to EVL intrinsics or something)?</div>
</div>
</blockquote>
<p>We could untie the mask length from the data length:</p>
<p> %result = call <scalable 4 x float>
@llvm.evl.fsub.v4f32(<scalable 4 x float> %x, <scalable 4
x float> %y, <scalable 1 x i1> %M, i32 %L)</p>
<p>would then indicate the the mask %M applies to groups of "4 / 1"
float elements.</p>
<p>- Simon<br>
</p>
<p><br>
</p>
<blockquote type="cite"
cite="mid:CAC2bXD7WZcoHbr_HTnJjbkt=WXKONArKNhCHiO9YuXaeFePhZA@mail.gmail.com">
<div dir="auto">
<div dir="auto">Jacob Lifshay</div>
</div>
<br>
<div class="gmail_quote">
<div dir="ltr">On Thu, Jan 31, 2019, 07:58 Simon Moll via
llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org"
moz-do-not-send="true">llvm-dev@lists.llvm.org</a> wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div text="#000000" bgcolor="#FFFFFF"> Hi,<br>
<br>
There is now an RFC for a roadmap to native vector
predication support in LLVM and a prototype implementation:<br>
<br>
<a class="m_-1502931027590774306moz-txt-link-freetext"
href="https://reviews.llvm.org/D57504" target="_blank"
rel="noreferrer" moz-do-not-send="true">https://reviews.llvm.org/D57504</a><br>
<br>
The prototype demonstrates:<br>
<br>
- Predicated vector intrinsics with an explicit mask and
vector length parameter on IR level.<br>
- First-class predicated SDNodes on ISel level. Mask and
vector length are value operands.<br>
- An incremental strategy to generalize
PatternMatch/InstCombine/InstSimplify and DAGCombiner to
work on both regular instructions and EVL intrinsics.<br>
- DAGCombiner example: FMA fusion.<br>
- InstCombine/InstSimplify example: FSub pattern re-writes.<br>
- Early experiments on the LNT test suite (Clang static
release, O3 -ffast-math) indicate that compile time on
non-EVL IR is not affected by the API abstractions in
PatternMatch, etc.<br>
<br>
We’d like to get your feedback, in particular on the
following to move forward:<br>
<br>
- Can we agree on EVL intrinsics as a transitional step to
predicated IR instructions?<br>
- Can we agree on native EVL SDNodes for CodeGen?<br>
- Are the changes to InstCombine/InstSimplify/DAGCombiner
and utility classes that go with it acceptable?<br>
<br>
Thanks<br>
Simon<span style="font-size:11pt;color:rgb(0,0,0);background-color:transparent;font-weight:400;font-style:normal;font-variant:normal;text-decoration:none;vertical-align:baseline;white-space:pre-wrap"></span><span style="font-size:11pt;color:rgb(0,0,0);background-color:transparent;font-weight:400;font-style:normal;font-variant:normal;text-decoration:none;vertical-align:baseline;white-space:pre-wrap"></span>
<pre class="m_-1502931027590774306moz-signature" cols="72">--
Simon Moll
Researcher / PhD Student
Compiler Design Lab (Prof. Hack)
Saarland University, Computer Science
Building E1.3, Room 4.31
Tel. +49 (0)681 302-57521 : <a class="m_-1502931027590774306moz-txt-link-abbreviated" href="mailto:moll@cs.uni-saarland.de" target="_blank" rel="noreferrer" moz-do-not-send="true">moll@cs.uni-saarland.de</a>
Fax. +49 (0)681 302-3065 : <a class="m_-1502931027590774306moz-txt-link-freetext" href="http://compilers.cs.uni-saarland.de/people/moll" target="_blank" rel="noreferrer" moz-do-not-send="true">http://compilers.cs.uni-saarland.de/people/moll</a></pre>
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</blockquote>
</div>
</blockquote>
<pre class="moz-signature" cols="72">--
Simon Moll
Researcher / PhD Student
Compiler Design Lab (Prof. Hack)
Saarland University, Computer Science
Building E1.3, Room 4.31
Tel. +49 (0)681 302-57521 : <a class="moz-txt-link-abbreviated" href="mailto:moll@cs.uni-saarland.de">moll@cs.uni-saarland.de</a>
Fax. +49 (0)681 302-3065 : <a class="moz-txt-link-freetext" href="http://compilers.cs.uni-saarland.de/people/moll">http://compilers.cs.uni-saarland.de/people/moll</a></pre>
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