<div dir="ltr">Dylan,<div>   Thanks for all your hard work!  Will need to test the latest and greatest! Looking forward to RFC soon, after a few more reviews,</div><div>Allen. </div></div><br><div class="gmail_quote"><div dir="ltr">On Sun, Jan 13, 2019 at 11:17 PM Dylan McKay <<a href="mailto:me@dylanmckay.io">me@dylanmckay.io</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div class="gmail-m_-8420659335184423560markdown-here-wrapper"><p style="margin:0px 0px 1.2em">Hello all,</p>
<p style="margin:0px 0px 1.2em">It is a near year and a new LLVM release; 7.0. It has been a while since the last AVR update email, the backend has become much better at handling complex programs.</p>
<p style="margin:0px 0px 1.2em">To that end, this is the first LLVM release than can successfully compile all of upstream Rust’s main compiler support library <code style="font-size:0.85em;font-family:Consolas,Inconsolata,Courier,monospace;margin:0px 0.15em;padding:0px 0.3em;white-space:pre-wrap;border:1px solid rgb(234,234,234);background-color:rgb(248,248,248);border-radius:3px;display:inline">libcore</code> without error. This was the main blocker in merging the <a href="https://github.com/avr-rust/rust" target="_blank">avr-rust</a> fork upstream.</p>
<p style="margin:0px 0px 1.2em">There have a few been more backend contributors this year, mostly coming from the avr-rust project.</p>
<p style="margin:0px 0px 1.2em">The vast majority of the changes this last year have been related to compilation bugfixes. We have been focusing on improving Rust support, which exposed a number of compilation bugs and C-only assumptions that have now been fixed. The amount of IR correctly accepted by the AVR backend has noticeably increased, including implementation of atomics and things not seen in C such as structs with zero size.</p>
<h1 id="gmail-m_-8420659335184423560frontends-supporting-avr" style="margin:1.3em 0px 1em;padding:0px;font-weight:bold;font-size:1.6em;border-bottom:1px solid rgb(221,221,221)">Frontends supporting AVR</h1>
<ul style="margin:1.2em 0px;padding-left:2em">
<li style="margin:0.5em 0px">clang</li>
<li style="margin:0.5em 0px">Rust</li><ul><li style="margin:0.5em 0px"><a href="https://github.com/avr-rust/" target="_blank">https://github.com/avr-rust/ </a></li><li style="margin:0.5em 0px">The fork has been updated to Rust master, supporting edition 2018</li></ul>
<li style="margin:0.5em 0px">Swift<br><ul><li>    <a href="http://swiftforarduino.com/" target="_blank">http://swiftforarduino.com/</a></li></ul></li>
<li style="margin:0.5em 0px">Go<br><ul><li>    <a href="https://github.com/aykevl/tinygo" target="_blank">https://github.com/aykevl/tinygo</a></li></ul></li>
</ul>
<h1 id="gmail-m_-8420659335184423560changes" style="margin:1.3em 0px 1em;padding:0px;font-weight:bold;font-size:1.6em;border-bottom:1px solid rgb(221,221,221)">Changes</h1>
<p style="margin:0px 0px 1.2em">Support for functions in nonzero address spaces has landed upstream</p>
<p style="margin:0px 0px 1.2em">Address space 0 is always RAM, address space 1 is always program/flash memory<br>In the past, functions could only be in address space 0, and thus the entire LLVM middlend acted on the unfound assumption that every functon pointer is in RAM… but it still mostly worked<br>Although a function pointer memory address would inherently load from address space 0 - RAM, but with a memory offset into flash memory!</p>
<p style="margin:0px 0px 1.2em">Now functions can be tagged with address spaces even at the textual IR level</p>
<p style="margin:0px 0px 1.2em">A bunch of uninteresting compilation assertion error fixes. Almost all of the changes fall into this category</p>
<p style="margin:0px 0px 1.2em">A few test suite fixes - thanks to several driveby contributors, it’s appreciated!</p>
<p style="margin:0px 0px 1.2em">i128 divisions are now supported via libgcc calls</p>
<h1 id="gmail-m_-8420659335184423560test-suite-stability" style="margin:1.3em 0px 1em;padding:0px;font-weight:bold;font-size:1.6em;border-bottom:1px solid rgb(221,221,221)">Test suite stability</h1>
<p style="margin:0px 0px 1.2em">The AVR backend and it’s test suite status has been decidedly more stable over the last year. In most backend-breaking LLVM changes, the AVR backend is updated at the same time as all the non-experimental backends.</p>
<p style="margin:0px 0px 1.2em">The backend is still marked as experimental, which means that no emails are sent out upon test failure. The AVR buildbot can be found on the staging buildmaster at <a href="http://lab.llvm.org:8014/builders/llvm-avr-linux" target="_blank">http://lab.llvm.org:8014/builders/llvm-avr-linux. 
</a></p>
<p style="margin:0px 0px 1.2em">My main priority is integration testing, which needs some work. I’ve got a project that integration tests the backend <a href="https://github.com/dylanmckay/avr-compiler-integration-tests" target="_blank">here</a>, but it cannot actually test LLVM trunk yet until <a href="https://reviews.llvm.org/D54334" target="_blank">D54334</a> ([AVR] Automatically link CRT and libgcc from the system avr-gcc) lands in clang, currently pending code review. The <a href="https://fabricesalvaire.github.io/simavr/doxygen/index.html" target="_blank">simavr</a> emulator has been very helpful here.</p>
<h1 id="gmail-m_-8420659335184423560backend-implementation-maintenance-pain-points" style="margin:1.3em 0px 1em;padding:0px;font-weight:bold;font-size:1.6em;border-bottom:1px solid rgb(221,221,221)">Backend implementation/maintenance pain points</h1>
<p style="margin:0px 0px 1.2em">The major pain points of an embedded processor backend with relatively exotic properties are mostly the same as they were a few years ago. This includes the greedy register allocator, which can sometimes struggle with the extremely constrains sometimes imposed by AVR.</p>
<p style="margin:0px 0px 1.2em">Another pain point is the DAG type legalizer, which currently assumes that arithmetic and logic operations only need to be split down into the smallest legal integer type. The implicit assumption is that hardware instructions are defined for every operation on the smallest legal integer type. The smallest legal integer type on AVR is 16-bit, which may be placed into 8-bit GPR pairs or 16-bit pointer registers. Only a small portion of the instruction set is 16-bit, with ADD, MUL, DIV, AND, OR, COM, etc only being defined on 8-bit general purpose registers. After DAG type legalization, >=32bit operation nodes are turned into multiple 16-bit operations, but instruction selection cannot ever match them because on AVR, most operations need to be split down once more to several 8-bit operations. The AVR workaround is to create a new pseudo instruction with a pattern for every 8-bit operation that operates on 16-bits. The <code style="font-size:0.85em;font-family:Consolas,Inconsolata,Courier,monospace;margin:0px 0.15em;padding:0px 0.3em;white-space:pre-wrap;border:1px solid rgb(234,234,234);background-color:rgb(248,248,248);border-radius:3px;display:inline">AVRExpandPseudoInsts</code> pass has a couple thousand lines manually expanding high-level 16-bit operations into hardware 8-bit instructions. A lot of complex AVR backend code could be deleted if LLVM had a way to split these operations down to the 8-bit level required.</p>
<h1 id="gmail-m_-8420659335184423560next-year" style="margin:1.3em 0px 1em;padding:0px;font-weight:bold;font-size:1.6em;border-bottom:1px solid rgb(221,221,221)">Next year</h1>
<p style="margin:0px 0px 1.2em">As mentioned above, integration testing is a big priority and will help improve stability of the backend, whilst also increasing confidence in committing future changes. The end goal is to have a constantly-running integration tester that tests every change in LLVM against simulated AVR hardware.</p>
<p style="margin:0px 0px 1.2em">I intend to write an RFC to LLVM-dev about the promotion of the backend from experimental to official in the coming weeks.</p>
<p style="margin:0px 0px 1.2em">Special thanks to all of the helpful contributors that wrote patches, reviewed code, fixed tests, raised issues, discussed problems, and updated the AVR backend at the same time alongside their LLVM API breaking commits ;)</p>
<p style="margin:0px 0px 1.2em">Happy 2019 everybody,<br>Dylan</p>
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