<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Nov 18, 2018, at 10:03 PM, Garfee Guan <<a href="mailto:garfee.guan@gmail.com" class="">garfee.guan@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="auto" class="">It does not work. I have tried to use the latest master today. But tblgen still give me information like </div><div dir="auto" class=""><br class=""></div><div dir="auto" class=""><div dir="auto" class="">error: Resources are defined for both SchedRead and its alias on processor MyArchModel</div><div dir="auto" class=""><br class=""></div><div dir="auto" class="">def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>; <br class=""></div><div dir="auto" class="">^<br class=""></div></div></div><div dir="ltr" class=""><br class=""></div><div class="">Unless I change "MyReadVector" to another read like "MyReadVector1", it would not work. Debugging into tblgen, there is no path to handle multiplle latencies for same Read...</div><div class=""><br class=""></div><div class="">Anyway as you reminded, I am searching for more Target and am looking into Pierre's change (I finally notice that he has a patch associated within the thread already :-) If it is feasible, I will try to make any suitable change back upstream)</div><div class=""><br class=""></div><div class="">-Garfee</div></div></div></div></blockquote><div><br class=""></div>I see what you mean. I thought the problem was with multiple latencies associated with a single definition: ReadAdvance<Read1, #, [Write1, Write2]>. There definitely should be some way to make this work. If you can upstream the patch that would be fantastic.</div><div>-Andy</div><div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Sat, Nov 17, 2018, 10:42 AM Andrew Trick <<a href="mailto:atrick@apple.com" target="_blank" class="">atrick@apple.com</a> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class=""><br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Nov 16, 2018, at 6:31 PM, Garfee Guan <<a href="mailto:garfee.guan@gmail.com" rel="noreferrer" target="_blank" class="">garfee.guan@gmail.com</a>> wrote:</div><br class="m_3101147901976302971gmail-m_3229694805414925795m_1009311763779090970Apple-interchange-newline"><div class=""><div dir="auto" class=""><div class="">Thanks Andrew. I have tried with recent tblgen, ReadAdvance would not work for multiple latencies. Maybe I should make improvement into tblgen if <span style="white-space:pre-wrap;font-family:sans-serif" class="">Pierre-Andre does not have the change anymore.</span></div><div dir="auto" class=""><font face="sans-serif" class=""><span style="white-space:pre-wrap" class=""><br class=""></span></font></div><div dir="auto" class=""><font face="sans-serif" class=""><span style="white-space:pre-wrap" class="">However, I just a little curious about the situation I met. The hardware forwording may fail for different reasons, which different register read may have different latencies, depending both on the register reader and writer. I am freshman into tblgen. So I wonder if any other Target already has other way to describe that .<br class=""></span></font></div></div></div></blockquote><div class=""><br class=""></div><div class="">Does this work for you?</div><div class=""><br class=""></div>// Forward from a vector op (normal, add, mul) to a non-store.<br class="">def : ReadAdvance<MyReadVector, 5, [WriteVector]>; <br class="">def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>;<br class="">def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector]>;</div><div class=""><br class=""></div><div class="">A ReadAdvance is associated with a pair of write resource -> read resource. You can specify as many variants of read/write resources as you want, even using arbitrary C++ code inside a predicate. So, in theory I think that should be flexible enough.</div><div class=""><br class=""></div><div class="">You can search the in-tree targets to see where ReadAdvance definitions are used. Sorry, I’m not familiar with anything beyond that, but maybe someone else on the list has dealt with the same problem.</div><div class=""><br class=""></div><div class="">-Andy</div><div class=""><br class=""><blockquote type="cite" class=""><div class=""><div dir="auto" class=""><div dir="auto" class=""><div class="gmail_quote" dir="auto"><div dir="ltr" class="">On Fri, Nov 16, 2018, 8:00 AM Andrew Trick <<a href="mailto:atrick@apple.com" rel="noreferrer" target="_blank" class="">atrick@apple.com</a> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class=""><br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Nov 14, 2018, at 10:52 PM, Garfee Guan via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" rel="noreferrer noreferrer" target="_blank" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="m_3101147901976302971gmail-m_3229694805414925795m_1009311763779090970m_-1843593469856779474Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><h1 class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">Hi list,</span></font></h1><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">I happened to read below thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH.</span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><br class=""></font></div><div class=""><font face="times new roman, serif" size="2" class="">It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example:<br class=""><br class="">def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; }</font></div><div class=""><font face="times new roman, serif" size="2" class="">...</font></div><div class=""><font face="times new roman, serif" size="2" class="">def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }<br class=""></font></div><div class=""><span style="font-family:"times new roman",serif" class="">def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }</span> <font face="times new roman, serif" size="2" class=""><br class=""></font></div><div class=""><font face="times new roman, serif" size="2" class="">...</font></div><div class=""><font face="times new roman, serif" size="2" class=""><br class=""></font></div><div class=""><font face="times new roman, serif" size="2" class="">Here I defined 3 different Writes with same latency number. Below shows the forwarding.</font></div><div class=""><br class=""></div><div class=""><span style="font-family:"times new roman",serif" class="">def : ReadAdvance<MyReadVector, 5, [WriteVector]>;</span> <font face="times new roman, serif" size="2" class=""><br class="">def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector_3cycles]>;</font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector_5cycles]>;</span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">...</span></font></div><div class=""><div class=""><span style="font-family:"times new roman",serif" class="">def : ReadAdvance<MyReadStoreVector, 0, [WriteVector]>;</span> <font face="times new roman, serif" size="2" class=""><br class="">def : ReadAdvance<MyReadStoreVector, 0, [MyWriteAddVector_3cycles]>;</font></div><div class=""><font face="times new roman, serif" size="2" class="">def : ReadAdvance<MyReadStoreVector, 0, [MyWriteMulVector_5cycles]>;</font></div><div class=""><font face="times new roman, serif" size="2" class="">...</font></div><br class="m_3101147901976302971gmail-m_3229694805414925795m_1009311763779090970m_-1843593469856779474gmail-Apple-interchange-newline"></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">Basically my intention is to model that, for any non-store instruction which reads vector, it forwards vector write to: </span></font><span style="font-family:"times new roman",serif" class="">normally 1 cycle, </span><span style="font-family:"times new roman",serif" class="">3 cycles for my ADD, </span><span style="font-family:"times new roman",serif" class="">5 cycles for my MUL. </span><span style="font-family:"times new roman",serif" class="">But for any store instruction takes vector register as source, It can not forward. So the latency is kept as 6.</span></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class=""><br class=""></span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">Unfortunately, above code can not be compiled by tblgen. I am not sure if I really need per-write cycle count with ReadAdvance, or there is any existed method to meet my requirement. Anyway the latencies here seems to be decided by considering both </span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class=""><br class=""></span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">a) 3 kinds of Write, </span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">b) 2 kinds of Read. </span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class=""><br class=""></span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">Therefore I doubt if it can not be modeled with current tblgen implement.</span></font></div></div></div></div></div></div></div></div></blockquote><div class=""><br class=""></div><div class="">I’m not sure if the TableGen bug mentioned below was ever fixed.</div><div class=""><br class=""></div><div class="">It looks to me like this should work, but I haven’t tried it:</div><div class=""><br class=""></div><div class="">def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; }<br class="">def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }<br class="">def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } </div><div class=""><br class=""></div><div class="">// Forward from a vector op (normal, add, mul) to a non-store.<br class="">def : ReadAdvance<MyReadVector, 5, [WriteVector]>; <br class="">def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>;<br class="">def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector]>;<br class=""><br class=""></div><div class="">Additionally, you could do this but I don’t think it would have any effect at all:</div><div class=""><br class=""></div>// Forward from a vector op (normal, add, mul) to a store.<br class=""><div class="">def : ReadAdvance<MyReadStoreVector, 0, [WriteVector, MyWriteAddVector, MyWriteMulVector]>;<br class=""><br class=""></div><div class="">-Andy</div><div class=""><br class=""></div><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">--</span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">Garfee Guan,</span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">LLVM Compiler Backend Engineer</span></font></div><div class=""><font face="times new roman, serif" size="2" class=""><span style="font-weight:400" class="">Enflame Technology Co.</span></font></div><div class=""><font face="times new roman, serif" size="2" class="">Website: <a href="http://www.enflame-tech.com/" rel="noreferrer noreferrer" target="_blank" class="">http://www.enflame-tech.com/</a><br class=""></font></div><div class=""><font face="times new roman, serif" size="2" class=""><br class=""></font></div><div class=""><font face="times new roman, serif" size="2" class="">--------------------------------------------------------------------</font></div><h1 style="font-family:"Times New Roman"" class="">[llvm-dev] Per-write cycle count with ReadAdvance<br class=""></h1><b style="font-family:"Times New Roman";font-size:inherit" class="">Pierre-Andre Saulais via llvm-dev</b><span style="font-family:"Times New Roman";font-size:inherit" class=""> </span><a href="mailto:llvm-dev%40lists.llvm.org?Subject=Re%3A%20%5Bllvm-dev%5D%20Per-write%20cycle%20count%20with%20ReadAdvance&In-Reply-To=%3C565C3F99.9060206%40codeplay.com%3E" title="[llvm-dev] Per-write cycle count with ReadAdvance" style="font-family:"Times New Roman";font-size:inherit" rel="noreferrer noreferrer" target="_blank" class="">llvm-dev at lists.llvm.org </a><br style="font-family:"Times New Roman";font-size:inherit" class=""><i style="font-family:"Times New Roman";font-size:inherit" class="">Mon Nov 30 04:22:49 PST 2015</i><span style="font-family:"Times New Roman";font-size:inherit" class=""></span><div style="font-family:"Times New Roman";font-size:inherit" class=""><br class="m_3101147901976302971gmail-m_3229694805414925795m_1009311763779090970m_-1843593469856779474webkit-block-placeholder"></div><ul style="font-family:"Times New Roman";font-size:inherit" class=""><li class="">Previous message: <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/092870.html" rel="noreferrer noreferrer" target="_blank" class="">[llvm-dev] difference with autotools, cmake and ninja building methods</a></li><li class="">Next message: <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/092850.html" rel="noreferrer noreferrer" target="_blank" class="">[llvm-dev] LLVM Weekly - #100, Nov 30th 2015</a></li><li class=""><b class="">Messages sorted by:</b> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/date.html#92849" rel="noreferrer noreferrer" target="_blank" class="">[ date ]</a> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/thread.html#92849" rel="noreferrer noreferrer" target="_blank" class="">[ thread ]</a> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/subject.html#92849" rel="noreferrer noreferrer" target="_blank" class="">[ subject ]</a> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849" rel="noreferrer noreferrer" target="_blank" class="">[ author ]</a></li></ul><hr style="font-family:"Times New Roman";font-size:inherit" class=""><pre style="white-space:pre-wrap" class="">Hi all,
I am working on a backend that uses the ProcResource scheduling model
and one limitation I found is that while it is possible to specify
multiple SchedWrites in a ReadAdvance record, each write uses the same
cycle count. I tried writing multiple ReadAdvance records for the same
SchedRead, but tablegen does not seem to allow that.
It would be useful to have a per-write cycle count to model different
pipeline bypasses, where the cycle count depends on the (read, write)
pair and not just on the read.
Two possible solutions are: 1) changing the 'Cycles' field in
(Proc)ReadAdvance to be a list of int and 2) changing tablegen to allow
multiple (Proc)ReadAdvance records with the same read resource.
The former solution doesn't seem ideal as it requires repeating the
cycle count many times for targets that use long SchedWriteRes lists:
-def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
+def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI,
WriteISReg, WriteIEReg,WriteIS,
WriteID32,WriteID64,
WriteIM32,WriteIM64]>;
The latter is a bit more verbose when per-write cycle count is used, but
requires no change to existing targets. It is also easier to visually
match cycle counts to write types:
def : ReadAdvance<ReadFoo, 2, [WriteType1]>;
def : ReadAdvance<ReadFoo, 4, [WriteType2]>;
def : ReadAdvance<ReadFoo, 3, [WriteType3]>;
I have a patch for the second solution. Would that benefit any in-tree
target?
Thanks,
Pierre-Andre
--
Pierre-Andre Saulais
Principal Software Engineer, Compilers
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