<div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><h1 style="color:rgb(0,0,0)"><font face="times new roman, serif" size="2"><span style="font-weight:400">Hi list,</span></font></h1><div><font face="times new roman, serif" size="2"><span style="font-weight:400">I happened to read below thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH.</span></font></div><div><font face="times new roman, serif" size="2"><br></font></div><div><font face="times new roman, serif" size="2">It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example:<br><br>def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; }</font></div><div><font face="times new roman, serif" size="2">...</font></div><div><font face="times new roman, serif" size="2">def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }<br></font></div><div><span style="font-family:"times new roman",serif">def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; }</span> <font face="times new roman, serif" size="2"><br></font></div><div><font face="times new roman, serif" size="2">...</font></div><div><font face="times new roman, serif" size="2"><br></font></div><div><font face="times new roman, serif" size="2">Here I defined 3 different Writes with same latency number. Below shows the forwarding.</font></div><div><br></div><div><span style="font-family:"times new roman",serif">def : ReadAdvance<MyReadVector, 5, [WriteVector]>;</span> <font face="times new roman, serif" size="2"><br>def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector_3cycles]>;</font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector_5cycles]>;</span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">...</span></font></div><div><div><span style="font-family:"times new roman",serif">def : ReadAdvance<MyReadStoreVector, 0, [WriteVector]>;</span> <font face="times new roman, serif" size="2"><br>def : ReadAdvance<MyReadStoreVector, 0, [MyWriteAddVector_3cycles]>;</font></div><div><font face="times new roman, serif" size="2">def : ReadAdvance<MyReadStoreVector, 0, [MyWriteMulVector_5cycles]>;</font></div><div><font face="times new roman, serif" size="2">...</font></div><br class="gmail-Apple-interchange-newline"></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">Basically my intention is to model that, for any non-store instruction which reads vector, it forwards vector write to: </span></font><span style="font-family:"times new roman",serif">normally 1 cycle, </span><span style="font-family:"times new roman",serif">3 cycles for my ADD, </span><span style="font-family:"times new roman",serif">5 cycles for my MUL. </span><span style="font-family:"times new roman",serif">But for any store instruction takes vector register as source, It can not forward. So the latency is kept as 6.</span></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400"><br></span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">Unfortunately, above code can not be compiled by tblgen. I am not sure if I really need per-write cycle count with ReadAdvance, or there is any existed method to meet my requirement. Anyway the latencies here seems to be decided by considering both </span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400"><br></span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">a) 3 kinds of Write, </span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">b) 2 kinds of Read. </span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400"><br></span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">Therefore I doubt if it can not be modeled with current tblgen implement.</span></font></div><div><span style="font-family:"times new roman",serif"><br></span></div><div><span style="font-family:"times new roman",serif">Can you comment and help?</span></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400"><br></span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">--</span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">Garfee Guan,</span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">LLVM Compiler Backend Engineer</span></font></div><div><font face="times new roman, serif" size="2"><span style="font-weight:400">Enflame Technology Co.</span></font></div><div><font face="times new roman, serif" size="2">Website: <a href="http://www.enflame-tech.com/">http://www.enflame-tech.com/</a><br></font></div><div><font face="times new roman, serif" size="2"><br></font></div><div><font face="times new roman, serif" size="2">--------------------------------------------------------------------</font></div><h1 style="color:rgb(0,0,0);font-family:"Times New Roman"">[llvm-dev] Per-write cycle count with ReadAdvance<br></h1><b style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium">Pierre-Andre Saulais via llvm-dev</b><span style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium"> </span><a href="mailto:llvm-dev%40lists.llvm.org?Subject=Re%3A%20%5Bllvm-dev%5D%20Per-write%20cycle%20count%20with%20ReadAdvance&In-Reply-To=%3C565C3F99.9060206%40codeplay.com%3E" title="[llvm-dev] Per-write cycle count with ReadAdvance" style="font-family:"Times New Roman";font-size:medium">llvm-dev at lists.llvm.org </a><br style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium"><i style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium">Mon Nov 30 04:22:49 PST 2015</i><span style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium"></span><p style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium"></p><ul style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium"><li>Previous message: <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/092870.html">[llvm-dev] difference with autotools, cmake and ninja building methods</a></li><li>Next message: <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/092850.html">[llvm-dev] LLVM Weekly - #100, Nov 30th 2015</a></li><li><b>Messages sorted by:</b> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/date.html#92849">[ date ]</a> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/thread.html#92849">[ thread ]</a> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/subject.html#92849">[ subject ]</a> <a href="http://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849">[ author ]</a></li></ul><hr style="color:rgb(0,0,0);font-family:"Times New Roman";font-size:medium"><pre style="white-space:pre-wrap;color:rgb(0,0,0)">Hi all,
I am working on a backend that uses the ProcResource scheduling model
and one limitation I found is that while it is possible to specify
multiple SchedWrites in a ReadAdvance record, each write uses the same
cycle count. I tried writing multiple ReadAdvance records for the same
SchedRead, but tablegen does not seem to allow that.
It would be useful to have a per-write cycle count to model different
pipeline bypasses, where the cycle count depends on the (read, write)
pair and not just on the read.
Two possible solutions are: 1) changing the 'Cycles' field in
(Proc)ReadAdvance to be a list of int and 2) changing tablegen to allow
multiple (Proc)ReadAdvance records with the same read resource.
The former solution doesn't seem ideal as it requires repeating the
cycle count many times for targets that use long SchedWriteRes lists:
-def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
+def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI,
WriteISReg, WriteIEReg,WriteIS,
WriteID32,WriteID64,
WriteIM32,WriteIM64]>;
The latter is a bit more verbose when per-write cycle count is used, but
requires no change to existing targets. It is also easier to visually
match cycle counts to write types:
def : ReadAdvance<ReadFoo, 2, [WriteType1]>;
def : ReadAdvance<ReadFoo, 4, [WriteType2]>;
def : ReadAdvance<ReadFoo, 3, [WriteType3]>;
I have a patch for the second solution. Would that benefit any in-tree
target?
Thanks,
Pierre-Andre
--
Pierre-Andre Saulais
Principal Software Engineer, Compilers
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