<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">No worries. Most likely it's referring to the implementation they based EE on. It wouldn't surprise me if there's a de-facto standard derived from the popular MIPS implementations at the time. Almost everyone will have needed a COP0 with similar functionality and I expect most of the chips available were based on a fairly small number of implementations.<br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Oct 29, 2018, at 10:39, Dan Ravensloft <<a href="mailto:dan.ravensloft@gmail.com" class="">dan.ravensloft@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class="">Indeed, this appears to be a documentation issue in the EE instruction set manual; it's an EE specific opcode (EI is 0x42000038, DI is 0x42000039) mislabelled as being MIPS I, when that was never defined before MIPS32r2.<br class=""><br class="">My mistake, sorry about that.</div></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Mon, 29 Oct 2018 at 17:25, Daniel Sanders <<a href="mailto:daniel_l_sanders@apple.com" class="">daniel_l_sanders@apple.com</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word;line-break:after-white-space" class=""><br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On Oct 27, 2018, at 06:42, Dan Ravensloft via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank" class="">llvm-dev@lists.llvm.org</a>> wrote:</div><br class="m_8755305065133403617Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class="">So, I have been working on Clang for the PS2, and recently decided a different approach of pretending the very quirky EE is a MIPS II CPU.<br class=""><br class="">During this process, I found that Clang refused to compile some assembly code with the MIPS instructions <font face="monospace, monospace" class="">ei</font> and <font face="monospace, monospace" class="">di</font> (enable/disable interrupts):<div class=""><br class=""></div><div class=""><div class=""><font face="monospace, monospace" class="">src/glue.c:32:17: error: instruction requires a CPU feature not currently enabled</font></div><div class=""><font face="monospace, monospace" class=""> asm volatile ("di");</font></div><div class=""><font face="monospace, monospace" class=""> ^</font></div></div><div class=""><font face="monospace, monospace" class=""><br class=""></font></div><div class=""><font face="arial, helvetica, sans-serif" class="">Though I haven't bisected it in full, judging by this Godbolt (<a href="https://godbolt.org/z/iRVpzd" target="_blank" class="">https://godbolt.org/z/iRVpzd</a>), these instructions have been feature-locked (incorrectly, as it is a MIPS 1 instruction) ever since Clang 3.9 (3.8.x works okay). It's worth noting that the instructions work fine with MIPS32r2 and above.</font></div></div></div></div></div></blockquote><div class=""><br class=""></div><div class="">It's been a while but that's probably around the point I went through the instructions and made sure MIPS II - V worked correctly in the assembler and verified the behaviour against GNU AS using the available documentation and llvm-mc-disassembler-fuzzer to generate test cases. Before that, there was no MIPS II - V support in LLVM. MIPS I was excluded since there's no known usage of that ISA.</div><div class=""><br class=""></div><div class="">The architecture docs (<a href="https://www.mips.com/products/architectures/mips32-2/" target="_blank" class="">https://www.mips.com/products/architectures/mips32-2/</a>) say it was added in MIPS32r2. If it was defined before then then it's odd that that document doesn't define it for MIPS32r1. MIPS didn't have any of pre MIPS32 docs available so the earliest docs I could find at the time was for MIPS II - IV (<a href="https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf" target="_blank" class="">https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf</a>) which doesn't mention ei/di. Additionally, they're COP0 instructions and it's mentioned at <a href="https://en.wikipedia.org/wiki/MIPS_architecture" target="_blank" class="">https://en.wikipedia.org/wiki/MIPS_architecture</a> that COP0 is implementation defined for MIPS I - V. That being the case, ei/di for EE may be different from the MIPS32r2 one and should probably enabled for EE specifically rather than for MIPS II - V.</div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div dir="ltr" class=""><div class=""><font face="arial, helvetica, sans-serif" class="">I will try to bisect and possibly fix this bug.</font></div></div></div></div>
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