<div dir="ltr"><div class="gmail_extra">Hi,</div><div class="gmail_extra"><br></div><div class="gmail_extra"><div class="gmail_extra">mohamed messelka via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org">llvm-dev@lists.llvm.org</a>> writes:</div><div class="gmail_extra">> Hi all,</div><div class="gmail_extra">> I want to generate assembly code using Swing Modulo Scheduling in LLVM for many ALU (May could be Adders, multilayer</div><div class="gmail_extra">> ......), I need some help how I can do that, which commend I run? </div><div class="gmail_extra">> Also if possible more information about the scheduling and the register location ......, and which pass responsible about that</div><div class="gmail_extra">> and which LLVM version support Swing Modulo Scheduling.</div><div class="gmail_extra"><br></div><div class="gmail_extra">I'm not sure if I am the right person to reply.</div><div class="gmail_extra"><br></div><div class="gmail_extra">You can use MachinePipeliner which implements Swing Modulo Scheduling</div><div class="gmail_extra">from LLVM 6.0.</div><div class="gmail_extra">However, its target architecture is currently Hexagon only.</div><div class="gmail_extra">#I am creating a patch so that MachinePipeliner can be used for AArch64.</div><div class="gmail_extra"><br></div><div class="gmail_extra">If you are building Clang/LLVM without specifying 'LLVM_TARGETS_TO_BUILD',</div><div class="gmail_extra">then I think that you can check the operation of MachinePipeliner as</div><div class="gmail_extra">follows:</div><div class="gmail_extra"><br></div><div class="gmail_extra">  % llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -debug-only=pipeliner < swp-vmult.ll</div><div class="gmail_extra"><br></div><div class="gmail_extra">under llvm/test/CodeGen/Hexagon.</div><div class="gmail_extra"><br></div><div class="gmail_extra">If your target machine is using 'ItineraryClasses' to describe the</div><div class="gmail_extra">machine model for scheduling, I think that MachinePipeliner using</div><div class="gmail_extra">'DFAPacketizer' is easy to use without additional work.</div><div class="gmail_extra">In the file 'llvm/include/llvm/Target/TargetSchedule.td', there is a</div><div class="gmail_extra">description of how to describe the schedule model of the target</div><div class="gmail_extra">machine.</div><div class="gmail_extra">Otherwise, you need to implement 'SwingSchedulerDAG::calculateResMII'</div><div class="gmail_extra">for managing hardware resources, 'SMSchedule::insert' for reserving</div><div class="gmail_extra">hardware resources, etc. in MachinePipeliner for your target machine.</div><div class="gmail_extra"><br></div><div class="gmail_extra">Because MachinePipeliner implements Swing Modulo Scheduling, it<br></div><div class="gmail_extra">generates kernel code considering register pressure.</div><div class="gmail_extra">However, this does not guarantee that spill code will not be generated</div><div class="gmail_extra">in the kernel in the subsequent register allocation pass.</div><div class="gmail_extra">Therefore, when a loop body is large, it is necessary to divide the</div><div class="gmail_extra">loop considering hardware resources(for example, the number of</div><div class="gmail_extra">registers) of the target machine.</div><div class="gmail_extra">However, I do not think that there is a pass to execute its task now</div><div class="gmail_extra">properly.</div><div class="gmail_extra"><br></div><div class="gmail_extra">Best regards,</div><div class="gmail_extra">--</div><div class="gmail_extra">--------------------------------------</div><div class="gmail_extra">Masaki Arai</div></div></div>