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<div class="">Hi Chandler,</div>
<div class=""><br class="">
</div>
<div class="">I've just uploaded a sequence of patches that implement a similar technique for</div>
<div class="">AArch64.</div>
<div class="">A small difference of approach is that I went for introducing an intrinsic that</div>
<div class="">can make any integer or pointer value "speculation-safe", i.e. the intrinsic</div>
<div class="">returns the value of its only parameter when correctly speculating, and returns</div>
<div class="">0 when miss-speculating.</div>
<div class="">The intrinsic is close to what Philip Reames suggested on</div>
<div class=""><a href="https://reviews.llvm.org/D41761" class="">https://reviews.llvm.org/D41761</a>.</div>
<div class=""><br class="">
</div>
<div class="">Then a later patch (D49072) adds automatic mitigation by inserting the intrinsic</div>
<div class="">in necessary locations.</div>
<div class=""><br class="">
</div>
<div class="">I believe this approach has the advantage that:</div>
<div class="">a) it makes it possible to only insert a mitigation in specific locations if</div>
<div class=""> the programmer is capable of inserting intrinsics manually.</div>
<div class="">b) it becomes easier to explore different options for implementing automatic</div>
<div class=""> protection - it's just a matter of writing different ways on how the</div>
<div class=""> intrinsic is injected into the program. See D49072 for how this is relatively</div>
<div class=""> easy.</div>
<div class=""><br class="">
</div>
<div class="">I've split the patches according to the following functionality:</div>
<div class="">- LLVM: <a href="https://reviews.llvm.org/D49069:" class="">https://reviews.llvm.org/D49069:</a> Introduce control flow speculation tracking for AArch64.</div>
<div class="">- LLVM: <a href="https://reviews.llvm.org/D49070:" class="">https://reviews.llvm.org/D49070:</a> Introduce llvm.speculation_safe_value intrinsic.</div>
<div class="">- LLVM: <a href="https://reviews.llvm.org/D49071:" class="">https://reviews.llvm.org/D49071:</a> Enable lowering of llvm.speculation_safe_value to DSB/ISB pair.</div>
<div class="">- LLVM: <a href="https://reviews.llvm.org/D49072:" class="">https://reviews.llvm.org/D49072:</a> Enable automatic mitigation against control flow speculation.</div>
<div class="">- Clang: <a href="https://reviews.llvm.org/D49073:" class="">https://reviews.llvm.org/D49073:</a> Introducing __builtin_speculation_safe_value.</div>
<div class=""><br class="">
</div>
<div class="">I'll be on a long holiday soon, so there may be delays to me reacting on review feedback.</div>
<div class=""><br class="">
</div>
<div class="">Thanks,</div>
<div class=""><br class="">
</div>
<div class="">Kristof</div>
<div class=""><br class="">
</div>
<div>
<blockquote type="cite" class="">
<div class="">On 23 Mar 2018, at 11:56, Chandler Carruth via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" class="">llvm-dev@lists.llvm.org</a>> wrote:</div>
<br class="Apple-interchange-newline">
<div class="">
<div dir="ltr" class="">Hello all,
<div class=""><br class="">
</div>
<div class="">I've been working for the last month or so on a comprehensive mitigation approach to variant #1 of Spectre. There are a bunch of reasons why this is desirable:</div>
<div class="">- Critical software that is unlikely to be easily hand-mitigated (or where the performance tradeoff isn't worth it) will have a compelling option.</div>
<div class="">- It gives us a baseline on performance for hand-mitigation.</div>
<div class="">- Combined with opt-in or opt-out, it may give simpler hand-mitigation.</div>
<div class="">- It is instructive to see *how* to mitigate code patterns.</div>
<div class=""><br class="">
</div>
<div class="">A detailed design document is available for commenting here:</div>
<div class=""><a href="https://docs.google.com/document/d/1wwcfv3UV9ZnZVcGiGuoITT_61e_Ko3TmoCS3uXLcJR0/edit" class="">https://docs.google.com/document/d/1wwcfv3UV9ZnZVcGiGuoITT_61e_Ko3TmoCS3uXLcJR0/edit</a></div>
<div class="">(I pasted this in markdown format at the bottom of the email as well.)<br class="">
</div>
<div class=""><br class="">
</div>
<div class="">I have also published a very early prototype patch that implements this design:</div>
<div class=""><a href="https://reviews.llvm.org/D44824" class="">https://reviews.llvm.org/D44824</a></div>
<div class="">This is the patch I've used to collect the performance data on the approach. It should be fairly functional but is a long way from being ready to review in detail, much less land. I'm posting so folks can start seeing the overall approach and
can play with it if they want. Grab it here:</div>
<div class=""><br class="">
</div>
<div class="">Comments are very welcome! I'd like to keep the doc and this thread focused on discussion of the high-level technique for hardening, and the code review thread for discussion of the techniques used to implement this in LLVM.</div>
<div class=""><br class="">
</div>
<div class="">Thanks all!</div>
<div class="">-Chandler</div>
<div class="">
<div class=""><br class="">
</div>
<div class="">--------</div>
<div class="">
<div class=""># Speculative Load Hardening</div>
<div class=""><br class="">
</div>
<div class="">### A Spectre Variant #1 Mitigation Technique</div>
<div class=""><br class="">
</div>
<div class="">Author: Chandler Carruth - [<a href="mailto:chandlerc@google.com" class="">chandlerc@google.com</a>](mailto:<a href="mailto:chandlerc@google.com" class="">chandlerc@google.com</a>)</div>
<div class=""><br class="">
</div>
<div class="">## Problem Statement</div>
<div class=""><br class="">
</div>
<div class="">Recently, Google Project Zero and other researchers have found information leak</div>
<div class="">vulnerabilities by exploiting speculative execution in modern CPUs. These</div>
<div class="">exploits are currently broken down into three variants:</div>
<div class="">* GPZ Variant #1 (a.k.a. Spectre Variant #1): Bounds check (or predicate) bypass</div>
<div class="">* GPZ Variant #2 (a.k.a. Spectre Variant #2): Branch target injection</div>
<div class="">* GPZ Variant #3 (a.k.a. Meltdown): Rogue data cache load</div>
<div class=""><br class="">
</div>
<div class="">For more details, see the Google Project Zero blog post and the Spectre research</div>
<div class="">paper:</div>
<div class="">* <a href="https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html" class="">
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html</a></div>
<div class="">* <a href="https://spectreattack.com/spectre.pdf" class="">https://spectreattack.com/spectre.pdf</a></div>
<div class=""><br class="">
</div>
<div class="">The core problem of GPZ Variant #1 is that speculative execution uses branch</div>
<div class="">prediction to select the path of instructions speculatively executed. This path</div>
<div class="">is speculatively executed with the available data, and may load from memory and</div>
<div class="">leak the loaded values through various side channels that survive even when the</div>
<div class="">speculative execution is unwound due to being incorrect. Mispredicted paths can</div>
<div class="">cause code to be executed with data inputs that never occur in correct</div>
<div class="">executions, making checks against malicious inputs ineffective and allowing</div>
<div class="">attackers to use malicious data inputs to leak secret data. Here is an example,</div>
<div class="">extracted and simplified from the Project Zero paper:</div>
<div class="">```</div>
<div class="">struct array {</div>
<div class=""> unsigned long length;</div>
<div class=""> unsigned char data[];</div>
<div class="">};</div>
<div class="">struct array *arr1 = ...; // small array</div>
<div class="">struct array *arr2 = ...; // array of size 0x400</div>
<div class="">unsigned long untrusted_offset_from_caller = ...;</div>
<div class="">if (untrusted_offset_from_caller < arr1->length) {</div>
<div class=""> unsigned char value = arr1->data[untrusted_offset_from_caller];</div>
<div class=""> unsigned long index2 = ((value&1)*0x100)+0x200;</div>
<div class=""> unsigned char value2 = arr2->data[index2]; </div>
<div class="">}</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">The key of the attack is to call this with `untrusted_offset_from_caller` that</div>
<div class="">is far outside of the bounds once the branch predictor is trained to predict</div>
<div class="">that it will be in-bounds. In that case, the body of the `if` will be executed</div>
<div class="">speculatively, and may read secret data into `value` and leak it via</div>
<div class="">a cache-timing side channel when a dependent access is made to populate</div>
<div class="">`value2`.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">## High Level Mitigation Approach</div>
<div class=""><br class="">
</div>
<div class="">While several approaches are being actively pursued to mitigate specific</div>
<div class="">branches and/or loads inside especially risky software (most notably various OS</div>
<div class="">kernels), these approaches require manual and/or static analysis aided auditing</div>
<div class="">of code and explicit source changes to apply the mitigation. They are unlikely</div>
<div class="">to scale well to large applications. We are proposing a comprehensive mitigation</div>
<div class="">approach that would apply automatically across an entire program rather than</div>
<div class="">through manual changes to the code. While this is likely to have a high</div>
<div class="">performance cost, some applications may be in a good position to take this</div>
<div class="">performance / security tradeoff.</div>
<div class=""><br class="">
</div>
<div class="">The specific technique we propose is to cause loads to be checked using</div>
<div class="">branchless code to ensure that they are executing along a valid control flow</div>
<div class="">path. Consider the following C-pseudo-code representing the core idea of</div>
<div class="">a predicate guarding potentially invalid loads:</div>
<div class="">```</div>
<div class="">void leak(int data);</div>
<div class="">void example(int* pointer1, int* pointer2) {</div>
<div class=""> if (condition) {</div>
<div class=""> // ... lots of code ...</div>
<div class=""> leak(*pointer1);</div>
<div class=""> } else {</div>
<div class=""> // ... more code ...</div>
<div class=""> leak(*pointer2);</div>
<div class=""> }</div>
<div class="">}</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This would get transformed into something resembling the following:</div>
<div class="">```</div>
<div class="">uintptr_t all_ones_mask = std::numerical_limits<uintptr_t>::max();</div>
<div class="">uintptr_t all_zeros_mask = 0;</div>
<div class="">void leak(int data);</div>
<div class="">void example(int* pointer1, int* pointer2) {</div>
<div class=""> uintptr_t predicate_state = all_ones_mask;</div>
<div class=""> if (condition) {</div>
<div class=""> predicate_state = !condition ? all_zeros_mask : predicate_state;</div>
<div class=""> // ... lots of code ...</div>
<div class=""> //</div>
<div class=""> // Harden the pointer so it can't be loaded</div>
<div class=""> pointer1 &= predicate_state;</div>
<div class=""> leak(*pointer1);</div>
<div class=""> } else {</div>
<div class=""> predicate_state = condition ? all_zeros_mask : predicate_state;</div>
<div class=""> // ... more code ...</div>
<div class=""> //</div>
<div class=""> // Alternative: Harden the loaded value</div>
<div class=""> int value2 = *pointer2 & predicate_state;</div>
<div class=""> leak(value2);</div>
<div class=""> }</div>
<div class="">}</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">The result should be that if the `if (condition) {` branch is mis-predicted,</div>
<div class="">there is a *data* dependency on the condition used to zero out any pointers</div>
<div class="">prior to loading through them or to zero out all of the loaded bits. Even though</div>
<div class="">this code pattern may still execute speculatively, *invalid* speculative</div>
<div class="">executions are prevented from leaking secret data from memory (but note that</div>
<div class="">this data might still be loaded in safe ways, and some regions of memory are</div>
<div class="">required to not hold secrets, see below for detailed limitations). This approach</div>
<div class="">only requires the underlying hardware have a way to implement a branchless and</div>
<div class="">unpredicted conditional update of a register's value. All modern architectures</div>
<div class="">have support for this, and in fact such support is necessary to correctly</div>
<div class="">implement constant time cryptographic primitives.</div>
<div class=""><br class="">
</div>
<div class="">Crucial properties of this approach:</div>
<div class="">* It does not attempt to prevent any particular side-channel from working. This</div>
<div class=""> is important as there are an unknown number of potential side channels and we</div>
<div class=""> expect to continue discovering more. Instead, it prevents the read of secret</div>
<div class=""> data in the first place.</div>
<div class="">* It accumulates the predicate state, protecting even in the face of nested</div>
<div class=""> *correctly* predicted control flows.</div>
<div class="">* It uses a *destructive* or *non-reversible* modification of the address loaded</div>
<div class=""> to prevent an attacker from reversing the check using attacker-controlled</div>
<div class=""> offsets to the pointer.</div>
<div class="">* It does not completely block speculative execution, and merely prevents</div>
<div class=""> *mis*-speculated paths from leaking secrets from memory (and stalls</div>
<div class=""> speculation until this can be determined).</div>
<div class="">* It is completely general and makes no fundamental assumptions about the</div>
<div class=""> underlying architecture other than the ability to do branchless conditional</div>
<div class=""> data updates and a lack of value prediction.</div>
<div class="">* It does not require programmers to identify all possible secret data or</div>
<div class=""> information leaks.</div>
<div class=""><br class="">
</div>
<div class="">Limitations of this approach:</div>
<div class="">* It requires re-compiling source code to insert hardening instruction</div>
<div class=""> sequences. Only software compiled in this mode is protected.</div>
<div class="">* The performance is heavily dependent on a particular architecture's</div>
<div class=""> implementation strategy. We outline a potential x86 implementation below and</div>
<div class=""> characterize its performance.</div>
<div class="">* It does not defend against secret data already loaded from memory and residing</div>
<div class=""> in registers. Code dealing with this, e.g cryptographic routines, already have</div>
<div class=""> patterns to scrub registers of secret data, but these patterns must also be</div>
<div class=""> made unconditional.</div>
<div class="">* To achieve reasonable performance, many loads may not be checked, such as</div>
<div class=""> those with compile-time fixed addresses. This primarily consists of accesses</div>
<div class=""> at compile-time constant offsets of global and local variables. Code which</div>
<div class=""> needs this protection and intentionally stores secret data must ensure the</div>
<div class=""> memory regions used for secret data are necessarily dynamic mappings or heap</div>
<div class=""> allocations. This is an area which can be tuned to provide more comprehensive</div>
<div class=""> protection at the cost of performance.</div>
<div class="">* Hardened loads may still load valid addresses if not attacker-controlled</div>
<div class=""> addresses. To prevent these from reading secret data, the low 2gb of the</div>
<div class=""> address space and 2gb above and below any executable pages should be</div>
<div class=""> protected.</div>
<div class=""><br class="">
</div>
<div class="">Credit:</div>
<div class="">* The core idea of tracing mis-speculation through data and marking pointers to</div>
<div class=""> block mis-speculated loads was developed as part of a HACS 2018 discussion</div>
<div class=""> with several individuals.</div>
<div class="">* Core idea of masking out loaded bits was part of the original mitigation</div>
<div class=""> suggested by Jann Horn when these attacks were reported.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">### Indirect Branches, Calls, and Returns</div>
<div class=""><br class="">
</div>
<div class="">It is possible to attack control flow other than conditional branches with</div>
<div class="">variant #1 style mispredictions.</div>
<div class="">* A prediction towards a hot call target of a virtual method can lead to it</div>
<div class=""> being speculatively executed when an expected type is used (often called "type</div>
<div class=""> confusion").</div>
<div class="">* A hot case may be speculatively executed due to prediction instead of the</div>
<div class=""> correct case for a switch statement implemented as a jump table.</div>
<div class="">* A hot common return address may be predicted incorrectly when returning from</div>
<div class=""> a function.</div>
<div class=""><br class="">
</div>
<div class="">These code patterns are also vulnerable to Spectre variant #2, and as such are</div>
<div class="">best mitigated with</div>
<div class="">a [retpoline](<a href="https://support.google.com/faqs/answer/7625886" class="">https://support.google.com/faqs/answer/7625886</a>) on x86 platforms.</div>
<div class="">When a mitigation technique like retpoline is used, speculation simply cannot</div>
<div class="">proceed through an indirect control flow edge (or it cannot be mispredicted in</div>
<div class="">the case of a filled RSB) and so it is also protected from variant #1 style</div>
<div class="">attacks. However, some architectures, micro-architectures, or vendors do not</div>
<div class="">employ the retpoline mitigation, and on future x86 hardware (both Intel and AMD)</div>
<div class="">it is expected to become unnecessary due to hardware-based mitigation.</div>
<div class=""><br class="">
</div>
<div class="">When not using a retpoline, these edges will need independent protection from</div>
<div class="">variant #1 style attacks. The analogous approach to that used for conditional</div>
<div class="">control flow should work:</div>
<div class="">```</div>
<div class="">uintptr_t all_ones_mask = std::numerical_limits<uintptr_t>::max();</div>
<div class="">uintptr_t all_zeros_mask = 0;</div>
<div class="">void leak(int data);</div>
<div class="">void example(int* pointer1, int* pointer2) {</div>
<div class=""> uintptr_t predicate_state = all_ones_mask;</div>
<div class=""> switch (condition) {</div>
<div class=""> case 0:</div>
<div class=""> predicate_state = (condition != 0) ? all_zeros_mask : predicate_state;</div>
<div class=""> // ... lots of code ...</div>
<div class=""> //</div>
<div class=""> // Harden the pointer so it can't be loaded</div>
<div class=""> pointer1 &= predicate_state;</div>
<div class=""> leak(*pointer1);</div>
<div class=""> break;</div>
<div class=""><br class="">
</div>
<div class=""> case 1:</div>
<div class=""> predicate_state = (condition != 1) ? all_zeros_mask : predicate_state;</div>
<div class=""> // ... more code ...</div>
<div class=""> //</div>
<div class=""> // Alternative: Harden the loaded value</div>
<div class=""> int value2 = *pointer2 & predicate_state;</div>
<div class=""> leak(value2);</div>
<div class=""> break;</div>
<div class=""><br class="">
</div>
<div class=""> // ...</div>
<div class=""> }</div>
<div class="">}</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">The core idea remains the same: validate the control flow using data-flow and</div>
<div class="">use that validation to check that loads cannot leak information along</div>
<div class="">misspeculated paths. Typically this involves passing the desired target of such</div>
<div class="">control flow across the edge and checking that it is correct afterwards. Note</div>
<div class="">that while it is tempting to think that this mitigates variant #2 attacks, it</div>
<div class="">does not. Those attacks go to arbitrary gadgets that don't include the checks.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">## Implementation Details</div>
<div class=""><br class="">
</div>
<div class="">There are a number of complex details impacting the implementation of this</div>
<div class="">technique, both on a particular architecture and within a particular compiler.</div>
<div class="">We discuss proposed implementation techniques for the x86 architecture and the</div>
<div class="">LLVM compiler. These are primarily to serve as an example, as other</div>
<div class="">implementation techniques are very possible.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">### x86 Implementation Details</div>
<div class=""><br class="">
</div>
<div class="">On the x86 platform we break down the implementation into three core components:</div>
<div class="">accumulating the predicate state through the control flow graph, checking the</div>
<div class="">loads, and checking control transfers between procedures.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">#### Accumulating Predicate State</div>
<div class=""><br class="">
</div>
<div class="">Consider baseline x86 instructions like the following, which test three</div>
<div class="">conditions and if all pass, loads data from memory and potentially leaks it</div>
<div class="">through some side channel:</div>
<div class="">```</div>
<div class=""># %bb.0: # %entry</div>
<div class=""> pushq %rax</div>
<div class=""> testl %edi, %edi</div>
<div class=""> jne .LBB0_4</div>
<div class=""># %bb.1: # %then1</div>
<div class=""> testl %esi, %esi</div>
<div class=""> jne .LBB0_4</div>
<div class=""># %bb.2: # %then2</div>
<div class=""> testl %edx, %edx</div>
<div class=""> je .LBB0_3</div>
<div class="">.LBB0_4: # %exit</div>
<div class=""> popq %rax</div>
<div class=""> retq</div>
<div class="">.LBB0_3: # %danger</div>
<div class=""> movl (%rcx), %edi</div>
<div class=""> callq leak</div>
<div class=""> popq %rax</div>
<div class=""> retq</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">When we go to speculatively execute the load, we want to know whether any of the</div>
<div class="">dynamically executed predicates have been mis-speculated. To track that, along</div>
<div class="">each conditional edge, we need to track the data which would allow that edge to</div>
<div class="">be taken. On x86, this data is stored in the flags register used by the</div>
<div class="">conditional jump instruction. Along both edges after this fork in control flow,</div>
<div class="">the flags register remains alive and contains data that we can use to build up</div>
<div class="">our accumulated predicate state. We accumulate it using the x86 conditional move</div>
<div class="">instruction which also reads the flag registers where the state resides. These</div>
<div class="">conditional move instructions are known to not be predicted on any x86</div>
<div class="">processors, making them immune to misprediction that could reintroduce the</div>
<div class="">vulnerability. When we insert the conditional moves, the code ends up looking</div>
<div class="">like the following:</div>
<div class="">```</div>
<div class=""># %bb.0: # %entry</div>
<div class=""> pushq %rax</div>
<div class=""> xorl %eax, %eax # Zero out initial predicate state.</div>
<div class=""> movq $-1, %r8 # Put all-ones mask into a register.</div>
<div class=""> testl %edi, %edi</div>
<div class=""> jne .LBB0_1</div>
<div class=""># %bb.2: # %then1</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> testl %esi, %esi</div>
<div class=""> jne .LBB0_1</div>
<div class=""># %bb.3: # %then2</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> testl %edx, %edx</div>
<div class=""> je .LBB0_4</div>
<div class="">.LBB0_1:</div>
<div class=""> cmoveq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> popq %rax</div>
<div class=""> retq</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> ...</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">Here we create the "empty" or "correct execution" predicate state by zeroing</div>
<div class="">`%rax`, and we create a constant "incorrect execution" predicate value by</div>
<div class="">putting `-1` into `%r8`. Then, along each edge coming out of a conditional</div>
<div class="">branch we do a conditional move that in a correct execution will be a no-op, but</div>
<div class="">if mis-speculated, will replace the `%rax` with the value of `%r8`.</div>
<div class="">Misspeculating any one of the three predicates will cause `%rax` to hold the</div>
<div class="">"incorrect execution" value from `%r8` as we preserve incoming values when</div>
<div class="">execution is correct rather than overwriting it.</div>
<div class=""><br class="">
</div>
<div class="">We now have a value in `%rax` in each basic block that indicates if at some</div>
<div class="">point previously a predicate was mispredicted. And we have arranged for that</div>
<div class="">value to be particularly effective when used below to harden loads.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Indirect Call, Branch, and Return Predicates</div>
<div class=""><br class="">
</div>
<div class="">(Not yet implemented.)</div>
<div class=""><br class="">
</div>
<div class="">There is no analogous flag to use when tracing indirect calls, branches, and</div>
<div class="">returns. The predicate state must be accumulated through some other means.</div>
<div class="">Fundamentally, this is the reverse of the problem posed in CFI: we need to check</div>
<div class="">where we came from rather than where we are going. For function-local jump</div>
<div class="">tables, this is easily arranged by testing the input to the jump table within</div>
<div class="">each destination:</div>
<div class="">```</div>
<div class=""> pushq %rax</div>
<div class=""> xorl %eax, %eax # Zero out initial predicate state.</div>
<div class=""> movq $-1, %r8 # Put all-ones mask into a register.</div>
<div class=""> jmpq *.LJTI0_0(,%rdi,8) # Indirect jump through table.</div>
<div class="">.LBB0_2: # %<a href="http://sw.bb/" class="">sw.bb</a></div>
<div class=""> testq $0, %rdi # Validate index used for jump table.</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> ...</div>
<div class=""> jmp _Z4leaki # TAILCALL</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_3: # %sw.bb1</div>
<div class=""> testq $1, %rdi # Validate index used for jump table.</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> ...</div>
<div class=""> jmp _Z4leaki # TAILCALL</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_5: # %sw.bb10</div>
<div class=""> testq $2, %rdi # Validate index used for jump table.</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> ...</div>
<div class=""> jmp _Z4leaki # TAILCALL</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class=""> .section .rodata,"a",@progbits</div>
<div class=""> .p2align 3</div>
<div class="">.LJTI0_0:</div>
<div class=""> .quad .LBB0_2</div>
<div class=""> .quad .LBB0_3</div>
<div class=""> .quad .LBB0_5</div>
<div class=""> ...</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">Returns have a simple mitigation technique on x86-64 (or other ABIs which have</div>
<div class="">what is called a "red zone" region beyond the end of the stack). This region is</div>
<div class="">guaranteed to be preserved across interrupts and context switches, making the</div>
<div class="">return address used in returning to the current code remain on the stack and</div>
<div class="">valid to read. We can emit code in the caller to verify that a return edge was</div>
<div class="">not mispredicted:</div>
<div class="">```</div>
<div class=""> callq other_function</div>
<div class="">return_addr:</div>
<div class=""> testq -8(%rsp), return_addr # Validate return address.</div>
<div class=""> cmovneq %r8, %rax # Update predicate state.</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">For an ABI without a "red zone" (and thus unable to read the return address from</div>
<div class="">the stack), mitigating returns face similar problems to calls below.</div>
<div class=""><br class="">
</div>
<div class="">Indirect calls (and returns in the absence of a red zone ABI) pose the most</div>
<div class="">significant challenge to propagate. The simplest technique would be to define</div>
<div class="">a new ABI such that the intended call target is passed into the called function</div>
<div class="">and checked in the entry. Unfortunately, new ABIs are quite expensive to deploy</div>
<div class="">in C and C++. While the target function could be passed in TLS, we would still</div>
<div class="">require complex logic to handle a mixture of functions compiled with and without</div>
<div class="">this extra logic (essentially, making the ABI backwards compatible). Currently,</div>
<div class="">we suggest using retpolines here and will continue to investigate ways of</div>
<div class="">mitigating this.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Optimizations, Alternatives, and Tradeoffs</div>
<div class=""><br class="">
</div>
<div class="">Merely accumulating predicate state involves significant cost. There are several</div>
<div class="">key optimizations we employ to minimize this and various alternatives that</div>
<div class="">present different tradeoffs in the generated code.</div>
<div class=""><br class="">
</div>
<div class="">First, we work to reduce the number of instructions used to track the state:</div>
<div class="">* Rather than inserting a `cmovCC` instruction along every conditional edge in</div>
<div class=""> the original program, we track each set of condition flags we need to capture</div>
<div class=""> prior to entering each basic block and reuse a common `cmovCC` sequence for</div>
<div class=""> those.</div>
<div class=""> * We could further reuse suffixes when there are multiple `cmovCC`</div>
<div class=""> instructions required to capture the set of flags. Currently this is</div>
<div class=""> believed to not be worth the cost as paired flags are relatively rare and</div>
<div class=""> suffixes of them are exceedingly rare.</div>
<div class="">* A common pattern in x86 is to have multiple conditional jump instructions that</div>
<div class=""> use the same flags but handle different conditions. Naively, we could consider</div>
<div class=""> each fallthrough between them an "edge" but this causes a much more complex</div>
<div class=""> control flow graph. Instead, we accumulate the set of conditions necessary for</div>
<div class=""> fallthrough and use a sequence of `cmovCC` instructions in a single</div>
<div class=""> fallthrough edge to track it.</div>
<div class=""><br class="">
</div>
<div class="">Second, we trade register pressure for simpler `cmovCC` instructions by</div>
<div class="">allocating a register for the "bad" state. We could read that value from memory</div>
<div class="">as part of the conditional move instruction, however, this creates more</div>
<div class="">micro-ops and requires the load-store unit to be involved. Currently, we place</div>
<div class="">the value into a virtual register and allow the register allocator to decide</div>
<div class="">when the register pressure is sufficient to make it worth spilling to memory and</div>
<div class="">reloading.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">#### Hardening Loads</div>
<div class=""><br class="">
</div>
<div class="">Once we have the predicate accumulated into a special value for correct vs.</div>
<div class="">mis-speculated, we need to apply this to loads in a way that ensures they do not</div>
<div class="">leak secret data. There are two primary techniques for this: we can either</div>
<div class="">harden the loaded value to prevent observation, or we can harden the address</div>
<div class="">itself to prevent the load from occuring. These have significantly different</div>
<div class="">performance tradeoffs.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Hardening loaded values</div>
<div class=""><br class="">
</div>
<div class="">The most appealing way to harden loads is to mask out all of the bits loaded.</div>
<div class="">The key requirement is that for each bit loaded, along the mis-speculated path</div>
<div class="">that bit is always fixed at either 0 or 1 regardless of the value of the bit</div>
<div class="">loaded. The most obvious implementation uses either an `and` instruction with an</div>
<div class="">all-zero mask along mis-speculated paths and an all-one mask along correct</div>
<div class="">paths, or an `or` instruction with an all-one mask along mis-speculated paths</div>
<div class="">and an all-zero mask along correct paths. Other options become less appealing</div>
<div class="">such as multiplying by zero or one, or multiple shift instructions. For reasons</div>
<div class="">we elaborate on below, we end up suggesting you use `or` with an all-ones mask,</div>
<div class="">making the x86 instruction sequence look like the following:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> movl (%rsi), %edi # Load potentially secret data from %rsi.</div>
<div class=""> orl %eax, %edi</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">Other useful patterns may be to fold the load into the `or` instruction itself</div>
<div class="">at the cost of a register-to-register copy.</div>
<div class=""><br class="">
</div>
<div class="">There are some challenges with deploying this approach:</div>
<div class="">1. Many loads on x86 are folded into other instructions. Separating them would</div>
<div class=""> add very significant and costly register pressure with prohibitive</div>
<div class=""> performance cost.</div>
<div class="">2. Loads may not target a general purpose register requiring extra instructions</div>
<div class=""> to map the state value into the correct register class, and potentially more</div>
<div class=""> expensive instructions to mask the value in some way.</div>
<div class="">3. The flags registers on x86 are very likely to be live, and challenging to</div>
<div class=""> preserve cheaply.</div>
<div class="">4. There are many more values loaded than pointers & indices used for loads. As</div>
<div class=""> a consequence, hardening the result of a load requires substantially more</div>
<div class=""> instructions than hardening the address of the load (see below).</div>
<div class=""><br class="">
</div>
<div class="">Despite these challenges, hardening the result of the load critically allows</div>
<div class="">the load to proceed and thus has dramatically less impact on the total</div>
<div class="">speculative / out-of-order potential of the execution. There are also several</div>
<div class="">interesting techniques to try and mitigate these challenges and make hardening</div>
<div class="">the results of loads viable in at least some cases. However, we generally</div>
<div class="">expect to fall back when unprofitable from hardening the loaded value to the</div>
<div class="">next approach of hardening the address itself.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Loads folded into data-invariant operations can be hardened after the operation</div>
<div class=""><br class="">
</div>
<div class="">The first key to making this feasible is to recognize that many operations on</div>
<div class="">x86 are "data-invariant". That is, they have no (known) observable behavior</div>
<div class="">differences due to the particular input data. These instructions are often used</div>
<div class="">when implementing cryptographic primitives dealing with private key data</div>
<div class="">because they are not believed to provide any side-channels. Similarly, we can</div>
<div class="">defer hardening until after them as they will not in-and-of-themselves</div>
<div class="">introduce a speculative execution side-channel. This results in code sequences</div>
<div class="">that look like:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> addl (%rsi), %edi # Load and accumulate without leaking.</div>
<div class=""> orl %eax, %edi</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">While an addition happens to the loaded (potentially secret) value, that</div>
<div class="">doesn't leak any data and we then immediately harden it.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Hardening of loaded values deferred down the data-invariant expression graph</div>
<div class=""><br class="">
</div>
<div class="">We can generalize the previous idea and sink the hardening down the expression</div>
<div class="">graph across as many data-invariant operations as desirable. This can use very</div>
<div class="">conservative rules for whether something is data-invariant. The primary goal</div>
<div class="">should be to handle multiple loads with a single hardening instruction:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> addl (%rsi), %edi # Load and accumulate without leaking.</div>
<div class=""> addl 4(%rsi), %edi # Continue without leaking.</div>
<div class=""> addl 8(%rsi), %edi</div>
<div class=""> orl %eax, %edi # Mask out bits from all three loads.</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Preserving the flags while hardening loaded values on Haswell, Zen, and newer processors</div>
<div class=""><br class="">
</div>
<div class="">Sadly, there are no useful instructions on x86 that apply a mask to all 64 bits</div>
<div class="">without touching the flag registers. However, we can harden loaded values that</div>
<div class="">are narrower than a word (fewer than 32-bits on 32-bit systems and fewer than</div>
<div class="">64-bits on 64-bit systems) by zero-extending the value to the full word size</div>
<div class="">and then shifting right by at least the number of original bits using the BMI2</div>
<div class="">`shrx` instruction:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> addl (%rsi), %edi # Load and accumulate 32 bits of data.</div>
<div class=""> shrxq %rax, %rdi, %rdi # Shift out all 32 bits loaded.</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">Because on x86 the zero-extend is free, this can efficiently harden the loaded</div>
<div class="">value.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Hardening the address of the load</div>
<div class=""><br class="">
</div>
<div class="">When hardening the loaded value is inapplicable, most often because the</div>
<div class="">instruction directly leaks information (like `cmp` or `jmpq`), we switch to</div>
<div class="">hardening the _address_ of the load instead of the loaded value. This avoids</div>
<div class="">increasing register pressure by unfolding the load or paying some other high</div>
<div class="">cost.</div>
<div class=""><br class="">
</div>
<div class="">To understand how this works in practice, we need to examine the exact</div>
<div class="">semantics of the x86 addressing modes which, in its fully general form, looks</div>
<div class="">like `(%base,%index,scale)offset`. Here `%base` and `%index` are 64-bit</div>
<div class="">registers that can potentially be any value, and may be attacker controlled,</div>
<div class="">and `scale` and `offset` are fixed immediate values. `scale` must be `1`, `2`,</div>
<div class="">`4`, or `8`, and `offset` can be any 32-bit sign extended value. The exact</div>
<div class="">computation performed to find the address is then: `%base + (scale * %index) +</div>
<div class="">offset` under 64-bit 2's complement modular arithmetic.</div>
<div class=""><br class="">
</div>
<div class="">One issue with this approach is that, after hardening, the `%base + (scale *</div>
<div class="">%index)` subexpression will compute a value near zero (`-1 + (scale * -1)`) and</div>
<div class="">then a large, positive `offset` will index into memory within the first two</div>
<div class="">gigabytes of address space. While these offsets are not attacker controlled,</div>
<div class="">the attacker could chose to attack a load which happens to have the desired</div>
<div class="">offset and then successfully read memory in that region. This significantly</div>
<div class="">raises the burden on the attacker and limits the scope of attack but does not</div>
<div class="">eliminate it. To fully close the attack we must work with the operating system</div>
<div class="">to preclude mapping memory in the low two gigabytes of address space.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### 64-bit load checking instructions</div>
<div class=""><br class="">
</div>
<div class="">We can use the following instruction sequences to check loads. We set up `%r8`</div>
<div class="">in these examples to hold the special value of `-1` which will be `cmov`ed over</div>
<div class="">`%rax` in mis-speculated paths.</div>
<div class=""><br class="">
</div>
<div class="">Single register addressing mode:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> orq %rax, %rsi # Mask the pointer if misspeculating.</div>
<div class=""> movl (%rsi), %edi</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">Two register addressing mode:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> orq %rax, %rsi # Mask the pointer if misspeculating.</div>
<div class=""> orq %rax, %rcx # Mask the index if misspeculating.</div>
<div class=""> movl (%rsi,%rcx), %edi</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This will result in a negative address near zero or in `offset` wrapping the</div>
<div class="">address space back to a small positive address. Small, negative addresses will</div>
<div class="">fault in user-mode for most operating systems, but targets which need the high</div>
<div class="">address space to be user accessible may need to adjust the exact sequence used</div>
<div class="">above. Additionally, the low addresses will need to be marked unreadable by the</div>
<div class="">OS to fully harden the load.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### RIP-relative addressing is even easier to break</div>
<div class=""><br class="">
</div>
<div class="">There is a common addressing mode idiom that is substantially harder to check:</div>
<div class="">addressing relative to the instruction pointer. We cannot change the value of</div>
<div class="">the instruction pointer register and so we have the harder problem of forcing</div>
<div class="">`%base + scale * %index + offset` to be an invalid address, by *only* changing</div>
<div class="">`%index`. The only advantage we have is that the attacker also cannot modify</div>
<div class="">`%base`. If we use the fast instruction sequence above, but only apply it to</div>
<div class="">the index, we will always access `%rip + (scale * -1) + offset`. If the</div>
<div class="">attacker can find a load which with this address happens to point to secret</div>
<div class="">data, then they can reach it. However, the loader and base libraries can also</div>
<div class="">simply refuse to map the heap, data segments, or stack within 2gb of any of the</div>
<div class="">text in the program, much like it can reserve the low 2gb of address space.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### The flag registers again make everything hard</div>
<div class=""><br class="">
</div>
<div class="">Unfortunately, the technique of using `orq`-instructions has a serious flaw on</div>
<div class="">x86. The very thing that makes it easy to accumulate state, the flag registers</div>
<div class="">containing predicates, causes serious problems here because they may be alive</div>
<div class="">and used by the loading instruction or subsequent instructions. On x86, the</div>
<div class="">`orq` instruction **sets** the flags and will override anything already there.</div>
<div class="">This makes inserting them into the instruction stream very hazardous.</div>
<div class="">Unfortunately, unlike when hardening the loaded value, we have no fallback here</div>
<div class="">and so we must have a fully general approach available.</div>
<div class=""><br class="">
</div>
<div class="">The first thing we must do when generating these sequences is try to analyze</div>
<div class="">the surrounding code to prove that the flags are not in fact alive or being</div>
<div class="">used. Typically, it has been set by some other instruction which just happens</div>
<div class="">to set the flags register (much like ours!) with no actual dependency. In those</div>
<div class="">cases, it is safe to directly insert these instructions. Alternatively we may</div>
<div class="">be able to move them earlier to avoid clobbering the used value.</div>
<div class=""><br class="">
</div>
<div class="">However, this may ultimately be impossible. In that case, we need to preserve</div>
<div class="">the flags around these instructions:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> pushfq</div>
<div class=""> orq %rax, %rcx # Mask the pointer if misspeculating.</div>
<div class=""> orq %rax, %rdx # Mask the index if misspeculating.</div>
<div class=""> popfq</div>
<div class=""> movl (%rcx,%rdx), %edi</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">Using the `pushf` and `popf` instructions saves the flags register around our</div>
<div class="">inserted code, but comes at a high cost. First, we must store the flags to the</div>
<div class="">stack and reload them. Second, this causes the stack pointer to be adjusted</div>
<div class="">dynamically, requiring a frame pointer be used for referring to temporaries</div>
<div class="">spilled to the stack, etc.</div>
<div class=""><br class="">
</div>
<div class="">On newer x86 processors we can use the `lahf` and `sahf` instructions to save</div>
<div class="">all of the flags besides the overflow flag in a register rather than on the</div>
<div class="">stack. We can then use `seto` and `add` to save and restore the overflow flag</div>
<div class="">in a register. Combined, this will save and restore flags in the same manner as</div>
<div class="">above but using two registers rather than the stack. That is still very</div>
<div class="">expensive if slightly less expensive than `pushf` and `popf` in most cases.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### A flag-less alternative on Haswell, Zen and newer processors</div>
<div class=""><br class="">
</div>
<div class="">Starting with the BMI2 x86 instruction set extensions available on Haswell and</div>
<div class="">Zen processors, there is an instruction for shifting that does not set any</div>
<div class="">flags: `shrx`. We can use this and the `lea` instruction to implement analogous</div>
<div class="">code sequences to the above ones. However, these are still very marginally</div>
<div class="">slower, as there are fewer ports able to dispatch shift instructions in most</div>
<div class="">modern x86 processors than there are for `or` instructions.</div>
<div class=""><br class="">
</div>
<div class="">Fast, single register addressing mode:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> shrxq %rax, %rsi, %rsi # Shift away bits if misspeculating.</div>
<div class=""> movl (%rsi), %edi</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This will collapse the register to zero or one, and everything but the offset</div>
<div class="">in the addressing mode to be less than or equal to 9. This means the full</div>
<div class="">address can only be guaranteed to be less than `(1 << 31) + 9`. The OS may wish</div>
<div class="">to protect an extra page of the low address space to account for this</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Optimizations</div>
<div class=""><br class="">
</div>
<div class="">A very large portion of the cost for this approach comes from checking loads in</div>
<div class="">this way, so it is important to work to optimize this. However, beyond making</div>
<div class="">the instruction sequences to *apply* the checks efficient (for example by</div>
<div class="">avoiding `pushfq` and `popfq` sequences), the only significant optimization is</div>
<div class="">to check fewer loads without introducing a vulnerability. We apply several</div>
<div class="">techniques to accomplish that.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Don't check loads from compile-time constant stack offsets</div>
<div class=""><br class="">
</div>
<div class="">We implement this optimization on x86 by skipping the checking of loads which</div>
<div class="">use a fixed frame pointer offset.</div>
<div class=""><br class="">
</div>
<div class="">The result of this optimization is that patterns like reloading a spilled</div>
<div class="">register or accessing a global field don't get checked. This is a very</div>
<div class="">significant performance win.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Don't check dependent loads</div>
<div class=""><br class="">
</div>
<div class="">A core part of why this mitigation strategy works is that it establishes a</div>
<div class="">data-flow check on the loaded address. However, this means that if the address</div>
<div class="">itself was already loaded using a checked load, there is no need to check a</div>
<div class="">dependent load provided it is within the same basic block as the checked load,</div>
<div class="">and therefore has no additional predicates guarding it. Consider code like the</div>
<div class="">following:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> movq (%rcx), %rdi</div>
<div class=""> movl (%rdi), %edx</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This will get transformed into:</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> orq %rax, %rcx # Mask the pointer if misspeculating.</div>
<div class=""> movq (%rcx), %rdi # Hardened load.</div>
<div class=""> movl (%rdi), %edx # Unhardened load due to dependent addr.</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This doesn't check the load through `%rdi` as that pointer is dependent on a</div>
<div class="">checked load already.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Protect large, load-heavy blocks with a single lfence</div>
<div class=""><br class="">
</div>
<div class="">It may be worth using a single `lfence` instruction at the start of a block</div>
<div class="">which begins with a (very) large number of loads that require independent</div>
<div class="">protection *and* which require hardening the address of the load. However, this</div>
<div class="">is unlikely to be profitable in practice. The latency hit of the hardening</div>
<div class="">would need to exceed that of an `lfence` when *correctly* speculatively</div>
<div class="">executed. But in that case, the `lfence` cost is a complete loss of speculative</div>
<div class="">execution (at a minimum). So far, the evidence we have of the performance cost</div>
<div class="">of using `lfence` indicates few if any hot code patterns where this trade off</div>
<div class="">would make sense.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">###### Tempting optimizations that break the security model</div>
<div class=""><br class="">
</div>
<div class="">Several optimizations were considered which didn't pan out due to failure to</div>
<div class="">uphold the security model. One in particular is worth discussing as many others</div>
<div class="">will reduce to it.</div>
<div class=""><br class="">
</div>
<div class="">We wondered whether only the *first* load in a basic block could be checked. If</div>
<div class="">the check works as intended, it forms an invalid pointer that doesn't even</div>
<div class="">virtual-address translate in the hardware. It should fault very early on in its</div>
<div class="">processing. Maybe that would stop things in time for the mis-speculated path to</div>
<div class="">fail to leak any secrets. This doesn't end up working because the processor is</div>
<div class="">fundamentally out-of-order, even in its speculative domain. As a consequence,</div>
<div class="">the attacker could cause the initial address computation itself to stall and</div>
<div class="">allow an arbitrary number of unrelated loads (including attacked loads of</div>
<div class="">secret data) to pass through.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">#### Interprocedural Checking</div>
<div class=""><br class="">
</div>
<div class="">Modern x86 processors may speculate into called functions and out of functions</div>
<div class="">to their return address. As a consequence, we need a way to check loads that</div>
<div class="">occur after a mis-speculated predicate but where the load and the</div>
<div class="">mis-speculated predicate are in different functions. In essence, we need some</div>
<div class="">interprocedural generalization of the predicate state tracking. A primary</div>
<div class="">challenge to passing the predicate state between functions is that we would</div>
<div class="">like to not require a change to the ABI or calling convention in order to make</div>
<div class="">this mitigation more deployable, and further would like code mitigated in this</div>
<div class="">way to be easily mixed with code not mitigated in this way and without</div>
<div class="">completely losing the value of the mitigation.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Embed the predicate state into the high bit(s) of the stack pointer</div>
<div class=""><br class="">
</div>
<div class="">We can use the same technique that allows hardening pointers to pass the</div>
<div class="">predicate state into and out of functions. The stack pointer is trivially</div>
<div class="">passed between functions and we can test for it having the high bits set to</div>
<div class="">detect when it has been marked due to mis-speculation. The callsite instruction</div>
<div class="">sequence looks like (assuming a mis-speculated state value of `-1`):</div>
<div class="">```</div>
<div class=""> ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_4: # %danger</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> shlq $47, %rax</div>
<div class=""> orq %rax, %rsp</div>
<div class=""> callq other_function</div>
<div class=""> movq %rsp, %rax</div>
<div class=""> sarq 63, %rax # Sign extend the high bit to all bits.</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This first puts the predicate state into the high bits of `%rsp` before calling</div>
<div class="">the function and then reads it back out of high bits of `%rsp` afterward. When</div>
<div class="">correctly executing (speculatively or not), these are all no-ops. When</div>
<div class="">misspeculating, the stack pointer will end up negative. We arrange for it to</div>
<div class="">remain a canonical address, but otherwise leave the low bits alone to allow</div>
<div class="">stack adjustments to proceed normally without disrupting this. Within the</div>
<div class="">called function, we can extract this predicate state and then reset it on</div>
<div class="">return:</div>
<div class="">```</div>
<div class="">other_function:</div>
<div class=""> # prolog</div>
<div class=""> callq other_function</div>
<div class=""> movq %rsp, %rax</div>
<div class=""> sarq 63, %rax # Sign extend the high bit to all bits.</div>
<div class=""> # ...</div>
<div class=""><br class="">
</div>
<div class="">.LBB0_N:</div>
<div class=""> cmovneq %r8, %rax # Conditionally update predicate state.</div>
<div class=""> shlq $47, %rax</div>
<div class=""> orq %rax, %rsp</div>
<div class=""> retq</div>
<div class="">```</div>
<div class=""><br class="">
</div>
<div class="">This approach is effective when all code is mitigated in this fashion, and can</div>
<div class="">even survive very limited reaches into unmitigated code (the state will</div>
<div class="">round-trip in and back out of an unmitigated function, it just won't be</div>
<div class="">updated). But it does have some limitations. There is a cost to merging the</div>
<div class="">state into `%rsp` and it doesn't insulate mitigated code from mis-speculation</div>
<div class="">in an unmitigated caller.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Rewrite API of internal functions to directly propagate predicate state</div>
<div class=""><br class="">
</div>
<div class="">(Not yet implemented.)</div>
<div class=""><br class="">
</div>
<div class="">We have the option with internal functions to directly adjust their API to</div>
<div class="">accept the predicate as an argument and return it. This is likely to be</div>
<div class="">marginally cheaper than embedding into `%rsp` for entering functions.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Use `lfence` to guard function transitions</div>
<div class=""><br class="">
</div>
<div class="">We know that an `lfence` instruction can be used to block speculation</div>
<div class="">completely and so we can use this stronger mitigation between functions. We</div>
<div class="">emit it in the entry block to handle calls, and prior to each return. This</div>
<div class="">approach also has the advantage of providing the strongest degree of mitigation</div>
<div class="">when mixed with unmitigated code by halting all mis-speculation entering a</div>
<div class="">function which is mitigated, regardless of what occured in the caller.</div>
<div class=""><br class="">
</div>
<div class="">However, experimental results indicate that the performance overhead of this</div>
<div class="">approach is very high for certain patterns of code. A classic example is any</div>
<div class="">form of recursive evaluation engine. The hot, rapid call and return sequences</div>
<div class="">exhibit dramatic performance loss when mitigated with `lfence`. This component</div>
<div class="">alone can regress performance by 2x or more.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Use an internal TLS location to pass predicate state</div>
<div class=""><br class="">
</div>
<div class="">We can define a special thread-local value to hold the predicate state between</div>
<div class="">functions. This avoids direct ABI implications by using a side channel between</div>
<div class="">callers and callees to communicate the predicate state. It also allows implicit</div>
<div class="">zero-initialization of the state, which allows non-checked code to be the first</div>
<div class="">code executed.</div>
<div class=""><br class="">
</div>
<div class="">However, this requires a load from TLS in the entry block, a store to TLS</div>
<div class="">before every call and every ret, and a load from TLS after every call. As a</div>
<div class="">consequence it is expected to be substantially more expensive even than using</div>
<div class="">`%rsp` and potentially `lfence` within the function entry block.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">##### Define a new ABI and/or calling convention</div>
<div class=""><br class="">
</div>
<div class="">We could define a new ABI and/or calling convention to explicitly pass the</div>
<div class="">predicate state in and out of functions. This may be interesting if none of the</div>
<div class="">alternatives have adequate performance, but it makes deployment and adoption</div>
<div class="">dramatically more complex, and potentially infeasible.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">## Alternative Mitigation Strategies</div>
<div class=""><br class="">
</div>
<div class="">[Most](<a href="https://lwn.net/Articles/743265/" class="">https://lwn.net/Articles/743265/</a>)</div>
<div class="">[discussion](<a href="https://lwn.net/Articles/744287/" class="">https://lwn.net/Articles/744287/</a>) on mitigating variant 1 attacks</div>
<div class="">focuses on mitigating specific known attackable components in the Linux kernel</div>
<div class="">(or other kernels) by manually rewriting the code to contain an instruction</div>
<div class="">sequence that is not vulnerable. For x86 systems this is done by either</div>
<div class="">injecting an `lfence` instruction along the code path which would leak data if</div>
<div class="">executed speculatively or by rewriting memory accesses to have branch-less</div>
<div class="">masking to a known safe region. On Intel systems, `lfence` [will prevent the</div>
<div class="">speculative load of secret</div>
<div class="">data](<a href="https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/Intel-Analysis-of-Speculative-Execution-Side-Channels.pdf" class="">https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/Intel-Analysis-of-Speculative-Execution-Side-Channels.pdf</a>).</div>
<div class="">On AMD systems `lfence` is currently a no-op, but can be made</div>
<div class="">dispatch-serializing by setting an MSR, and thus preclude mis-speculation of</div>
<div class="">the code path ([mitigation G-2 +</div>
<div class="">V1-1](<a href="https://developer.amd.com/wp-content/resources/Managing-Speculation-on-AMD-Processors.pdf)" class="">https://developer.amd.com/wp-content/resources/Managing-Speculation-on-AMD-Processors.pdf)</a>).</div>
<div class=""><br class="">
</div>
<div class="">However, this relies on finding and enumerating all possible points in code</div>
<div class="">which could be attacked to leak information. While in some cases static</div>
<div class="">analysis is effective at doing this at scale, in many cases it still relies on</div>
<div class="">human judgement to evaluate whether code might be vulnerable. Especially for</div>
<div class="">software systems which receive less detailed scrutiny but remain sensitive to</div>
<div class="">these attacks, this seems like an impractical security model. We need an</div>
<div class="">automatic and systematic mitigation strategy.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">### Automatic `lfence` on Conditional Edges</div>
<div class=""><br class="">
</div>
<div class="">A natural way to scale up the existing hand-coded mitigations is simply to</div>
<div class="">inject an `lfence` instruction into both the target and fallthrough</div>
<div class="">destinations of every conditional branch. This ensures that no predicate or</div>
<div class="">bounds check can be bypassed speculatively. However, the performance overhead</div>
<div class="">of this approach is, simply put, catastrophic. Yet it remains the only truly</div>
<div class="">"secure by default" approach known prior to this effort and serves as the</div>
<div class="">baseline for performance.</div>
<div class=""><br class="">
</div>
<div class="">One attempt to address the performance overhead of this and make it more</div>
<div class="">realistic to deploy is [MSVC's /Qspectre</div>
<div class="">switch](<a href="https://blogs.msdn.microsoft.com/vcblog/2018/01/15/spectre-mitigations-in-msvc/" class="">https://blogs.msdn.microsoft.com/vcblog/2018/01/15/spectre-mitigations-in-msvc/</a>).</div>
<div class="">Their technique is to use static analysis within the compiler to only insert</div>
<div class="">`lfence` instructions into conditional edges at risk of attack. However,</div>
<div class="">initial analysis (still under embargo) has shown that this analysis is</div>
<div class="">incomplete and only catches a small and limited subset of attackable patterns</div>
<div class="">which happen to resemble very closely the initial proofs of concept. As such,</div>
<div class="">while its performance is acceptable, it does not appear to be an adequate</div>
<div class="">systematic mitigation.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">## Performance Overhead</div>
<div class=""><br class="">
</div>
<div class="">The performance overhead of this style of comprehensive mitigation is very</div>
<div class="">high. However, it compares very favorably with previously recommended</div>
<div class="">approaches such as the `lfence` instruction. Just as users can restrict the</div>
<div class="">scope of `lfence` to control its performance impact, this mitigation technique</div>
<div class="">could be restricted in scope as well.</div>
<div class=""><br class="">
</div>
<div class="">However, it is important to understand what it would cost to get a fully</div>
<div class="">mitigated baseline. Here we assume targeting a Haswell (or newer) processor and</div>
<div class="">using all of the tricks to improve performance (so leaves the low 2gb</div>
<div class="">unprotected and +/- 2gb surrounding any PC in the program). We ran both</div>
<div class="">Google's microbenchmark suite and a large highly-tuned server built using</div>
<div class="">ThinLTO and PGO. All were built with `-march=haswell` to give access to BMI2</div>
<div class="">instructions, and benchmarks were run on large Haswell servers. We collected</div>
<div class="">data both with an `lfence`-based mitigation and load hardening as presented</div>
<div class="">here. The summary is that mitigating with load hardening is 1.77x faster than</div>
<div class="">mitigating with `lfence`, and the overhead of load hardening compared to a</div>
<div class="">normal program is likely between a 10% overhead and a 50% overhead with most</div>
<div class="">large applications seeing a 30% overhead or less.</div>
<div class=""><br class="">
</div>
<div class="">| Benchmark | `lfence` | Load Hardening | Mitigated Speedup |</div>
<div class="">| -------------------------------------- | -------: | -------------: | ----------------: |</div>
<div class="">| Google microbenchmark suite | -74.8% | -36.4% | **2.5x** |</div>
<div class="">| Large server QPS (using ThinLTO & PGO) | -62% | -29% | **1.8x** |</div>
<div class=""><br class="">
</div>
<div class="">Below is a visualization of the microbenchmark suite results which hels show the</div>
<div class="">distribution of results that is somewhat lost in the summary. The y-axis is</div>
<div class="">a log-scale speedup ratio of load hardening relative to `lfence` (up -> faster</div>
<div class="">-> better). Each box-and-whiskers represents one microbenchmark which may have</div>
<div class="">many different metrics measured. The red line marks the median, the box marks</div>
<div class="">the first and third quartiles, and the whiskers mark the min and max.</div>
<div class=""><br class="">
</div>
<div class=""></div>
<div class=""><br class="">
</div>
<div class="">We don't yet have benchmark data on SPEC or the LLVM test suite, but we can work</div>
<div class="">on getting that. Still, the above should give a pretty clear characterization of</div>
<div class="">the performance, and specific benchmarks are unlikely to reveal especially</div>
<div class="">interesting properties.</div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div class="">### Future Work: Fine Grained Control and API-Integration</div>
<div class=""><br class="">
</div>
<div class="">The performance overhead of this technique is likely to be very significant and</div>
<div class="">something users wish to control or reduce. There are interesting options here</div>
<div class="">that impact the implementation strategy used.</div>
<div class=""><br class="">
</div>
<div class="">One particularly appealing option is to allow both opt-in and opt-out of this</div>
<div class="">mitigation at reasonably fine granularity such as on a per-function basis,</div>
<div class="">including intelligent handling of inlining decisions -- protected code can be</div>
<div class="">prevented from inlining into unprotected code, and unprotected code will become</div>
<div class="">protected when inlined into protected code. For systems where only a limited set</div>
<div class="">of code is reachable by externally controlled inputs, it may be possible to</div>
<div class="">limit the scope of mitigation through such mechanisms without compromising the</div>
<div class="">application's overall security. The performance impact may also be focused in</div>
<div class="">a few key functions that can be hand-mitigated in ways that have lower</div>
<div class="">performance overhead while the remainder of the application receives automatic</div>
<div class="">protection.</div>
<div class=""><br class="">
</div>
<div class="">For both limiting the scope of mitigation or manually mitigating hot functions,</div>
<div class="">there needs to be some support for mixing mitigated and unmitigated code without</div>
<div class="">completely defeating the mitigation. For the first use case, it would be</div>
<div class="">particularly desirable that mitigated code remains safe when being called during</div>
<div class="">mis-speculation from unmitigated code.</div>
<div class=""><br class="">
</div>
<div class="">For the second use case, it may be important to connect the automatic mitigation</div>
<div class="">technique to explicit mitigation APIs such as what is described in</div>
<div class=""><a href="http://wg21.link/p0928" class="">http://wg21.link/p0928</a> (or any other eventual API) so that there is a clean way</div>
<div class="">to switch from automatic to manual mitigation without immediately exposing</div>
<div class="">a hole. However, the design for how to do this is hard to come up with until the</div>
<div class="">APIs are better established. We will revisit this as those APIs mature.</div>
</div>
</div>
</div>
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