<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
</head>
<body text="#000000" bgcolor="#FFFFFF">
<p>Hi,</p>
<p>It would still be nice to get some comment about this patch which
seems to help on SystemZ in the case where GRX32 pseudo
instructions are used. This means that the register eventually
ends up either in GR32 or GRH32 (low or high 32 bit subregs).<br>
</p>
<div class="moz-forward-container">Basically, I wonder if anyone has
tried this before and has any argument against this?<br>
<br>
Thanks,<br>
<br>
Jonas<br>
<br>
<br>
-------- Forwarded Message --------
<table class="moz-email-headers-table" cellspacing="0"
cellpadding="0" border="0">
<tbody>
<tr>
<th valign="BASELINE" align="RIGHT" nowrap="nowrap">Subject:
</th>
<td>InstrEmitter::CreateVirtualRegisters handling of
CopyToReg</td>
</tr>
<tr>
<th valign="BASELINE" align="RIGHT" nowrap="nowrap">Date: </th>
<td>Wed, 30 May 2018 15:02:57 +0200</td>
</tr>
<tr>
<th valign="BASELINE" align="RIGHT" nowrap="nowrap">From: </th>
<td>Jonas Paulsson <a class="moz-txt-link-rfc2396E" href="mailto:paulsson@linux.vnet.ibm.com"><paulsson@linux.vnet.ibm.com></a></td>
</tr>
<tr>
<th valign="BASELINE" align="RIGHT" nowrap="nowrap">To: </th>
<td>llvm-dev <a class="moz-txt-link-rfc2396E" href="mailto:llvm-dev@lists.llvm.org"><llvm-dev@lists.llvm.org></a></td>
</tr>
<tr>
<th valign="BASELINE" align="RIGHT" nowrap="nowrap">CC: </th>
<td>Ulrich Weigand <a class="moz-txt-link-rfc2396E" href="mailto:ulrich.weigand@de.ibm.com"><ulrich.weigand@de.ibm.com></a></td>
</tr>
</tbody>
</table>
<br>
<br>
<pre>Hi,
I wonder if anyone has any comment on a patch like:
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 65ee3816f84..4780f6f0e59 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -243,18 +243,21 @@ void InstrEmitter::CreateVirtualRegisters(SDNode
*Node,
if (!VRBase && !IsClone && !IsCloned)
for (SDNode *User : Node->uses()) {
if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).getNode() == Node &&
User->getOperand(2).getResNo() == i) {
unsigned Reg =
cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
- const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
- if (RegRC == RC) {
+ // Allow constraining the virtual register's class within
reason,
+ // just like what AddRegisterOperand will allow.
+ const TargetRegisterClass *ConstrainedRC
+ = MRI->constrainRegClass(Reg, RC, MinRCSize);
+ if (ConstrainedRC) {
VRBase = Reg;
MIB.addReg(VRBase, RegState::Define);
break;
}
}
}
}
Why do the register classes currently have to match exactly in this case?
It seems that these COPYs that now remain may end up in the same
register class, if the users require it. So why not constrain also here
directly, if this is done generally when the register is used as input?
/Jonas
</pre>
</div>
</body>
</html>