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<p class="MsoNormal">Hi list.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’m trying to enable sub-register liveness tracking for our target but I’m hitting the following assert on VirtRegRewriter::readsUndefSubreg:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"> assert(SubRegIdx != 0 && LI.hasSubRanges());<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The reason is that I have a register class of two bit predicates where only the low bit is allocatable so there’s only a single sub-register.<o:p></o:p></p>
<p class="MsoNormal">Now, MachineRegisterInfo only enables sub-reg liveness tracking for a class if it has at least two distinct sub-registers,
<o:p></o:p></p>
<p class="MsoNormal">so the live range cannot have sub-ranges in this case but instructions can read the single sub-reg nevertheless, which leads to this assertion failing.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Has anyone ran into this problem before or know of an in-tree target which has a similar construct?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal">Dvir<o:p></o:p></p>
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